EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 20
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Page 20
f
f
The V
1.8, 2.5, 3.0 and 3.3 V. Each bank can support a different voltage level. The V
serves as an input reference voltage for the voltage reference I/O standards and is
used mainly for a voltage bias and does not source or sink much current. The voltage
can be created with a regulator or a resistor divider network. If voltage reference I/O
standards are not used in the bank, the VREF pins are available as user I/O pins
In Cyclone III devices, Altera suggests that you use a linear regulator to power the
V
rails with the linear or switching regulators depending on the efficiency or cost
considerations.
To reduce system noise, it is important to ensure that the power supply is clean. Place
a ferrite bead and tantalum parallel capacitors where the power supply enters the
board’s power plane to filter out the noise to the power plane. Generally, the tantalum
capacitors are used for circuits which demand high stability in the capacitance values.
The ferrite bead should be connected in series between the power supply and the
power plane, while the capacitors are connected between the power plane and
ground, in parallel with each other. Decoupling depends on the design decoupling
requirements of the specific board.
For information on minimizing noise for power supplies, refer to
Board Layout Guidelines
Because the PLL contains analog components embedded in a digital device, there are
several considerations for designing the PLL power supply and minimizing jitter.
■
■
■
■
■
■
For more information about the decoupling strategy for Cyclone III power supplies,
refer to
CCA
To minimize jitter,
■
■
Make sure all VCCA and VCCD_PLL power pins are connected to a 2.5-V and 1.2-V
power supply respectively, regardless of whether you are using any PLL in the
device or not.
Use an isolated linear regulator to power the VCCA pin.
Connect the VCCD_PLL power pin to the quietest digital supply on the board.
Filter each VCCA and VCCD_PLL power pin with a decoupling circuit. Refer to
Cyclone III device pin-out for recommendation.
The GNDA pins should be connected to an isolated analog ground plane on the
board.
pins because they power the analog circuitry. You can power the digital voltage
CCIO
Run a thick trace (at least 20 mils) from the power supply to each VCCA pin.
Connect all VCCD_Pll power pins to the quietest digital supply on the board
Cyclone III Device Family Pin Connection Guidelines.
pin connections depend on the design’s I/O standards, and support 1.2, 1.5,
and
AN 315: Guidelines for Designing High-Speed FPGA PCBs.
© November 2008 Altera Corporation
Board Design Considerations
AN 224: High-Speed
REF
pin