EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 30
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Page 30
Design Recommendations
f
f
Intellectual Property
Altera and its third-party intellectual property (IP) partners offer a wide range of IP
cores. You can use these fully parameterizable and performance-optimized IP cores in
your design to save time on designing and testing as these IP cores are fully tested
and their functionality is proven. These IP cores are available for evaluation, allowing
you to verify the functionality and timing of the IP cores prior to purchasing a license.
For systems that have the Nios II embedded processor, you can write your C/C++
code for the processor. This is especially useful for system developers who are more
familiar in the C/C++ programming language than the hardware description
language.
For more information on the IP cores offered by Altera and its third-party IP partners,
refer to the Altera website at www.altera.com/products/ip/ipm-index.html.
Using Megafunctions
Altera provides parameterizable megafunctions that are optimized for Altera device
architectures. You can save design time with megafunctions instead of coding your
own logic. Additionally, the megafunctions provided by Altera may offer more
efficient logic synthesis and device implementation. You can scale the megafunction's
size and set various options with the parameters. Megafunctions include the library of
parameterized modules (LPM) and Altera device-specific megafunctions. You can
also take advantage of Altera and third-party IP and reference designs to save design
time.
The Quartus II MegaWizard Plug-In Manager provides an easy user interface to
customize megafunctions. You should build or change megafunction parameters
using the wizard to ensure that you set all the ports and parameters correctly.
For detailed information about specific megafunctions, refer to Quartus II Help or the
megafunction user guides on the
Good design practices especially those related to the clocks are essential in ensuring
that your design functions as intended.
Synchronous Design
In a synchronous design, the clock signal triggers signal transitions. On every active
edge of the clock, the data inputs of registers are sampled and transferred to outputs.
Use a single clock source to clock the registers in your design, as shown in
two cascaded registers are triggered on different clock sources or edges, there is a risk
that the second register will not have enough time to resolve the metastable output
from the first register because of setup time violation at the second register, and thus
will clock in an incorrect value.
User Guides
literature page.
© November 2008 Altera Corporation
Design and Compilation
Figure
3. If