EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 7
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Early System Planning
© November 2008 Altera Corporation
f
f
Cyclone III devices offer configuration data decompression and real-time remote
system upgrades to save configuration memory space and time. Support for these
configuration features varies depending on your configuration scheme. Cyclone III
devices also include optional configuration pins and a reconfiguration option that you
must determine at the start and set up in the Quartus II software, so that you have all
the information required for your board and system design. For the Quartus II
software settings and pins related to the configuration options that affect your board
and system design, refer to
Depending on the device densities and package options, you can configure
Cyclone III devices using one of the following five configuration schemes:
■
■
■
■
■
A selection of configuration scheme with different configuration voltage standards is
selected by driving the Cyclone III device’s MSEL pins either high or low. Depending
on the MSEL pin settings, you can either select a fast power-on reset (POR) time or a
standard POR time. The fast POR time supports fast wake-up time applications,
where it may be necessary for a device to wake up quickly to begin operation.
In Cyclone III devices, the supported configuration schemes differ for different device
densities and package options. For example, the EP3C16 device’s E144 package offers
the AS, PS, and JTAG schemes while its U484 package offers the AS, PS, FPP, AP, and
JTAG schemes.
For more information about the supported configuration schemes, refer to the
Cyclone III devices’
For complete information about the Cyclone III supported configuration schemes
across device densities and package options, configuration voltage standards and
POR time, ways to execute the required configuration schemes and all the necessary
option pin settings, including the MSEL pin settings, refer to the
Devices
For the new user of Altera device configuration schemes, the available choice of
configuration schemes and methods in which the configuration schemes can be set up
may be overwhelming. In general, Altera configuration schemes are categorized into
the following configuration schemes:
■
■
Active serial (AS)
Active parallel (AP)
Passive serial (PS)
Fast passive parallel (FPP)
Joint Test Action Group (JTAG)
Active configuration scheme
Passive configuration scheme
chapter in volume 1 of the Cyclone III Device Handbook.
Configuration
“Design and
Center.
Compilation”.
Configuring Cyclone III
Page 7