EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 180
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C10M164C8N PDF datasheet #6
- EP3C16F484C7N PDF datasheet #7
- Current page: 180 of 350
- Download datasheet (8Mb)
9–20
Cyclone III Device Handbook, Volume 1
Altera recommends putting a buffer before the DATA and DCLK output from the
master device to avoid signal strength and integrity issues. The buffer must not
significantly change the DATA-to-DCLK relationships or delay them with respect to
other AS signals (ASDI and nCS). Also, the buffer must only drive the slave devices to
ensure that the timing between the master device and the serial configuration device
is unaffected.
This configuration method supports both compressed and uncompressed .sofs.
Therefore, if the configuration bitstream size exceeds the capacity of a serial
configuration device, you can enable the compression feature in the .sof or you can
select a larger serial configuration device.
Guidelines for Connecting Serial Configuration Device to Cyclone III Device Family
on AS Interface
For single- and multi-device AS configurations, the board trace length and loading
between the supported serial configuration device and Cyclone III device family must
follow the recommendations listed in
Table 9–9. Maximum Trace Length and Loading for the AS Configuration
Estimating AS Configuration Time
AS configuration time is dominated by the time it takes to transfer data from the serial
configuration device to the Cyclone III device family. This serial interface is clocked
by the Cyclone III device family DCLK output (generated from an internal oscillator).
Equation 9–2
Cyclone III device family.
Equation 9–2.
Equation 9–3.
To estimate the typical configuration time, use the typical DCLK period shown in
Figure 9–7 on page
configuration time is 116.7 ms. Enabling compression reduces the amount of
configuration data that is sent to the Cyclone III device family, which also reduces
configuration time. On average, compression reduces configuration time by 50%.
RBF Size
3,500,000 bits
Device Family
Cyclone III
DATA[0]
AS Pins
DCLK
nCSO
ASDO
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
×
⎛
⎝
maximum DCLK period
- ----------------------------------------------------- -
×
and
⎛
⎝
50 ns
------------ -
1 bit
Equation 9–3
1 bit
9–22. With a typical DCLK period of 33.33 ns, the typical
Cyclone III Device Family to the Serial
⎞
⎠
Maximum Board Trace Length from the
=
Configuration Device (Inches)
175 ms
⎞
⎠
=
show the configuration time estimation for the
estimated maximum configuration time
10
10
10
10
Table
9–9.
© December 2009 Altera Corporation
Maximum Board Load (pF)
Configuration Features
15
30
30
30
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