EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 192
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C10M164C8N PDF datasheet #6
- EP3C16F484C7N PDF datasheet #7
- Current page: 192 of 350
- Download datasheet (8Mb)
9–32
Cyclone III Device Handbook, Volume 1
Figure 9–12
interfaces to minimize signal integrity issue.
Figure 9–12. Balanced Star Routing
Notes to
(1) Altera does not recommend M to exceed six inches as listed in
(2) Altera recommends using a balanced star routing. Try to keep the N length equal and as short as possible to minimize
Estimating the AP Configuration Time
AP configuration time is dominated by the time it takes to transfer data from the
parallel flash to the Cyclone III devices. This parallel interface is clocked by the
Cyclone III DCLK output (generated from an internal oscillator). As listed in
on page
20 MHz (50 ns). In word-wide cascade programming, the DATA[15..0] bus transfers
a 16-bit word and essentially cuts configuration time to approximately 1/16 of the AS
configuration time. Therefore, the maximum configuration time estimation for an
EP3C40 device (9,600,000 bits of uncompressed data) is defined in
Equation
Equation 9–4.
Equation 9–5.
To estimate a typical configuration time, use the typical DCLK period listed in
Table 9–8 on page
configuration time is 20 ms.
RBF Size
9,600,000 bits
reflection noise from the transmission line. The M length is applicable for this setup.
Figure
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
×
9–13, the DCLK minimum frequency when using the 40-MHz oscillator is
9–5.
⎛
⎝
maximum DCLK period
- ----------------------------------------------------- -
16 bits per DCLK cycle
shows the recommended balanced star routing for multiple bus master
9–12:
×
⎛
⎝
--------------- -
16 bits
50 ns
9–13. With a typical DCLK period of 33.33 ns, the typical
⎞
⎠
Master Device
Cyclone III
=
30 ms
DCLK
⎞
⎠
=
estimated maximum configuration time
M (1)
Table 9–12 on page
Numonyx Flash
Master Device
External
© December 2009 Altera Corporation
N (2)
N (2)
9–30.
Equation 9–4
Configuration Features
Table 9–8
and
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