EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 198
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C10M164C8N PDF datasheet #6
- EP3C16F484C7N PDF datasheet #7
- Current page: 198 of 350
- Download datasheet (8Mb)
9–38
Cyclone III Device Handbook, Volume 1
Figure 9–16
family is receiving the same configuration data.
Figure 9–16. Multi-Device PS Configuration When Both Devices Receive the Same Data
Notes to
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
(2) The nCEO pins of both devices are left unconnected or used as user I/O pins when configuring the same
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[0] and DCLK must fit the maximum overshoot
(MAX II Device or
Microprocessor)
External Host
chain. V
configuration data into multiple devices.
refer to
equation outlined in
ADDR
Figure
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Memory
Table 9–7 on page
CC
DATA[0]
must be high enough to meet the V
shows a multi-device PS configuration when both Cyclone III device
9–16:
10 k
V
“Configuration and JTAG Pin I/O Requirements” on page
CCIO
9–11. Connect the MSEL pins directly to V
(1) V
10 k
CCIO
GND
(1)
Buffers (4)
Cyclone III Device Family
IH
CONF_DONE
nSTATUS
nCE
DATA[0] (4)
nCONFIG
DCLK (4)
specification of the I/O on the device and the external host.
MSEL[3..0]
nCEO
(3)
N.C. (2)
CCA
or ground.
© December 2009 Altera Corporation
9–7.
GND
Cyclone III Device Family
CONF_DONE
nSTATUS
nCE
DATA[0] (4)
nCONFIG
DCLK (4)
Configuration Features
MSEL[3..0]
nCEO
N.C. (2)
(3)
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