EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 333
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C10M164C8N PDF datasheet #6
- EP3C16F484C7N PDF datasheet #7
- Current page: 333 of 350
- Download datasheet (8Mb)
Chapter 2: Cyclone III LS Device Data Sheet
Switching Characteristics
Table 2–20. Cyclone III LS Devices PLL Specifications
© December 2009
f
output)
t
t
t
t
t
t
t
t
t
t
f
Notes to
(1) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
(2) With 100-MHz scanclk frequency.
(3) Peak-to-peak jitter with a probability level of 10
(4) V
(5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less
(6) The V
f
OUT_EXT
OUTDUTY
LOCK
DLOCK
OUTJITTER_PERIOD_DEDC LK
OUTJITTER_CCJ _DEDCLK
OUTJITTER_PERIOD_IO
OUTJITTER_CCJ _IO
PLL_PSERR
ARESET
CONF IGPLL
SC ANC LK
OUT
(to global clock)
standard.
the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied.
than 200 ps.
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f
CC D_P LL
(external clock
(1)
Table
CO
Symbol
must be connected to V
frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the V
(3)
(3)
2–20:
(3)
Altera Corporation
(3)
PLL output frequency
PLL output frequency (–7 speed grade)
PLL output frequency (–8 speed grade)
Duty cycle for external clock output (when set to
50%)
Time required to lock from end of device
configuration
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
areset is deasserted)
Dedicated clock output period jitter F
F
Dedicated clock output cycle-to-cycle jitter
F
F
Regular I/O period jitter F
F
Regular I/O cycle-to-cycle jitter F
F
Accuracy of PLL phase shift
Minimum pulse width on areset signal.
Time required to reconfigure scan chains for PLLs
scanclk frequency
OUT
OUT
OUT
OUT
OUT
CC INT
< 100 MHz
≥ 100 MHz
< 100 MHz
< 100 MHz
< 100 MHz
through the decoupling capacitor and ferrite bead.
–12
(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to
Parameter
(Note 4)
OUT
≥ 100 MHz
OUT
(Part 2 of 2) (Preliminary)
≥ 100 MHz
OUT
≥ 100 MHz
Min
426
379
—
45
—
—
—
—
—
—
—
—
—
—
—
10
—
—
Cyclone III Device Handbook, Volume 2
Typ
3.5
(2)
—
—
—
50
—
—
—
—
—
—
—
—
—
—
—
—
—
VC O
402.5
Max
450
450
300
300
650
650
±50
100
55
30
30
75
75
—
—
specification.
1
1
scanclk
cycles
MHz
MHz
MHz
MHz
Unit
mUI
mUI
mUI
mUI
ms
ms
ps
ps
ps
ps
ps
ns
%
2–15
C O
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