EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 71
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C10M164C8N PDF datasheet #6
- EP3C16F484C7N PDF datasheet #7
- Current page: 71 of 350
- Download datasheet (8Mb)
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Clock Networks
GCLK Network Power Down
© December 2009
f
Altera Corporation
The inputs to the five clock control blocks on each side must be chosen from among
the following clock sources:
■
■
■
■
From the clock sources listed above, only two clock input pins, two PLL clock
outputs, one DPCLK or CDPCLK pin, and one source from internal logic can drive into
any given clock control block, as shown in
Out of these five inputs to any clock control block, the two clock input pins and two
PLL outputs are dynamically selected to feed a GCLK. The clock control block
supports static selection of the signal from internal logic.
Figure 5–3
the Cyclone III device family periphery.
Figure 5–3. Clock Control Blocks on Each Side of the Cyclone III Device Family
Note to
(1) The left and right sides of the device have two DPCLK pins; the top and bottom of the device have four DPCLK pins.
You can disable the Cyclone III device family GCLK (power down) by using both
static and dynamic approaches. In the static approach, configuration bits are set in the
configuration file generated by the Quartus II software, which automatically disables
unused GCLKs. The dynamic clock enable or disable feature allows internal logic to
control clock enable or disable of the GCLKs in the Cyclone III device family.
When a clock network is disabled, all the logic fed by the clock network is in an
off-state, thereby reducing the overall power consumption of the device. This function
is independent of the PLL and is applied directly on the clock network, as shown in
Figure 5–1 on page
You can set the input clock sources and the clkena signals for the GCLK
multiplexers through the Quartus II software using the ALTCLKCTRL megafunction.
For more information, refer to the
Four clock input pins
Five PLL counter outputs
Two DPCLK pins and two CDPCLK pins from both the left and right sides, and four
DPCLK pins and two CDPCLK pins from both the top and bottom
Five signals from internal logic
Figure
shows a simplified version of the five clock control blocks on each side of
5–3:
5–5.
Clock Input Pins
Internal Logic
PLL Outputs
CDPCLK
DPCLK
ALTCLKCTRL Megafunction User
2 or 4
4
5
2
5
Blocks on Each Side
Five Clock Control
of the Device
Figure 5–1 on page
Control
Clock
Block
5
Cyclone III Device Handbook, Volume 1
GCLK
5–5.
Guide.
(Note 1)
5–7
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