EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 137
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Standards Support
Figure 7–9. LVPECL DC-Coupled Termination
Differential SSTL I/O Standard Support in the Cyclone III Device Family
Figure 7–10. Differential SSTL Class I Interface
© December 2009
Output Buffer
f
Altera Corporation
LVPECL Transmitter
Figure 7–9
The differential SSTL I/O standard is a memory-bus standard used for applications
such as high-speed DDR SDRAM interfaces. The Cyclone III device family supports
differential SSTL-2 and SSTL-18 I/O standards. The differential SSTL I/O standard
requires two differential inputs with an external reference voltage (VREF) as well as an
external termination voltage (VTT) of 0.5 × V
connected. The differential SSTL output standard is only supported at PLL#_CLKOUT
pins using two single-ended SSTL output buffers (PLL#_CLKOUTp and
PLL#_CLKOUTn), with the second output programmed to have opposite polarity. The
differential SSTL input standard is supported on the GCLK pins only, treating
differential inputs as two single-ended SSTL and only decoding one of them.
For more information about the differential SSTL electrical specifications, refer to the
Cyclone III Device I/O Features
Cyclone III LS Device Data Sheet
Figure 7–10
shows the LVPECL DC-coupled termination.
shows the differential SSTL Class I interface.
50
50
chapter and the
chapters.
V
100
TT
CCIO
Cyclone III Device Data Sheet
Cyclone III Device Family
to which termination resistors are
LVPECL Receiver
V
TT
Cyclone III Device Handbook, Volume 1
Receiver
and
7–13