EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 205
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
© December 2009
Altera Corporation
Figure 9–21
circuit is similar to the FPP configuration circuit for a single device, except the
Cyclone III device family is cascaded for a multi-device configuration.
Figure 9–21. Multi-Device FPP Configuration Using an External Host
Notes to
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
(2) Connect the pull-up resistor to the V
(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],
(5) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[7..0] and DCLK must fit the maximum
In a multi-device FPP configuration, the nCE pin of the first device is connected to
GND while its nCEO pin is connected to the nCE pin of the next device in the chain.
The nCE input of the last device comes from the previous device while its nCEO pin is
left floating. After the first device completes configuration in a multi-device
configuration chain, its nCEO pin drives low to activate the nCE pin of the second
device, which prompts the second device to begin configuration. The second device in
the chain begins configuration in one clock cycle; therefore, the transfer of data
destinations is transparent to the MAX II device. All other configuration pins
(nCONFIG, nSTATUS, DCLK, DATA[7..0], and CONF_DONE) are connected to every
device in the chain. The configuration signals may require buffering to ensure signal
integrity and prevent clock skew problems. Ensure that the DCLK and DATA lines are
buffered. All devices initialize and enter user mode at the same time because all
device CONF_DONE pins are tied together.
All nSTATUS and CONF_DONE pins are tied together and if any device detects an error,
configuration stops for the entire chain and the entire chain must be reconfigured. For
example, if the first device flags an error on nSTATUS, it resets the chain by pulling its
nSTATUS pin low. This behavior is similar to a single device detecting an error.
chain. V
refer to
overshoot equation outlined in
(MAX II Device or
Microprocessor)
External Host
Figure
ADDR
Table 9–7 on page
CC
Memory
must be high enough to meet the V
shows how to configure multiple devices using a MAX II device. This
DATA[7..0]
9–21:
10 k
V CCIO (1) V CCIO (1)
9–11. Connect the MSEL pins directly to V
“Configuration and JTAG Pin I/O Requirements” on page
10 k
GND
CCIO
supply voltage of the I/O bank in which the nCE pin resides.
Buffers (5)
Cyclone III Device Family 1
IH
CONF_DONE
nSTATUS
nCE
DATA[7..0] (5)
nCONFIG
DCLK (5)
specification of the I/O on the device and the external host.
MSEL[3..0]
nCEO
(4)
CCA
or ground.
V CCIO (2)
Cyclone III Device Handbook, Volume 1
10 k
Cyclone III Device Family 2
CONF_DONE
nSTATUS
nCE
DATA[7..0] (5)
nCONFIG
DCLK (5)
9–7.
MSEL[3..0]
nCEO
N.C. (3)
(4)
9–45