EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 95
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C10M164C8N PDF datasheet #6
- EP3C16F484C7N PDF datasheet #7
- Current page: 95 of 274
- Download datasheet (6Mb)
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLL Reconfiguration
© December 2009
Altera Corporation
Table 5–10
PHASECOUNTERSELECT setting.
Table 5–10. Phase Counter Select Mapping
To perform one dynamic phase shift step, you must perform the following
procedures:
1. Set phaseupdown and phasecounterselect as required.
2. Assert phasestep for at least two scanclk cycles. Each phasestep pulse
3. Deassert phasestep.
4. Wait for phasedone to go high.
5. You can repeat steps
All signals are synchronous to scanclk, so they are latched on the scanclk edges
and must meet t
Figure 5–24. PLL Dynamic Phase Shift
Dynamic phase shifting can be repeated indefinitely. All signals are synchronous to
scanclk, so they must meet t
enables one phase shift.
shifts.
PHASECOUNTERSELECT [2]
phasecounterselect
lists the PLL counter selection based on the corresponding
phaseupdown
0
0
0
0
1
1
1
SU
phasestep
phasedone
or t
scanclk
H
requirements (with respect to the scanclk edges).
1
through
SU
or t
4
H
as many times as required to get multiple phase
[1]
0
0
1
1
0
0
1
requirements (with respect to scanclk edges).
[0]
0
1
0
1
0
1
0
Cyclone III Device Handbook, Volume 1
All Output Counters
C0 Counter
C1 Counter
C2 Counter
C3 Counter
C4 Counter
M Counter
Selects
5–31
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