EP3C55F484I7 Altera, EP3C55F484I7 Datasheet

IC CYCLONE III FPGA 55K 484 FBGA

EP3C55F484I7

Manufacturer Part Number
EP3C55F484I7
Description
IC CYCLONE III FPGA 55K 484 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C55F484I7

Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2396160
Number Of I /o
327
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Introduction
Device Selection
Device Feature Consideration
© November 2008 Altera Corporation
© November 2008
f
The Cyclone
FPGA family. Cyclone III FPGAs are built on Taiwan Semiconductor Manufacturing
Company's (TSMC) 65-nm low-power (LP) process technology with additional silicon
optimizations and software features to minimize power consumption. With this third
generation in the Cyclone series, Altera broadens the number of high volume,
cost-sensitive applications that can benefit from FPGAs. With a good design practice
and a clear understanding of the design flow of the Cyclone III device, your design
flow will be much easier. This design guideline summarizes not only the various
aspects of the Cyclone III device, but also the Quartus
should look into when designing with the Cyclone III devices.
This document covers the following topics:
This section provides the information for you to consider when choosing a Cyclone III
device for your system.
The Cyclone III device family offers over 5,000 logic elements (LEs) to nearly 120,000
LEs and is suitable for a wide range of applications. Always choose a device that has
more LEs than the estimated count for your design requirements so that you have
extra LEs either when you want to upgrade or expand your design. Consider having
additional LEs and memories for debugging purposes. Additional resources also
allow more flexibility with the Quartus II software for optimizing placement and
routing for maximum performance, lower power consumption or both.
the number of LEs, memory bits, multipliers, PLLs and global clock networks for
devices across the Cyclone III family.
For more information about the Cyclone III device resources across device density,
refer to the
Device Handbook.
“Device Selection” on page 1
“Early System Planning” on page 3
“Board Design Considerations” on page 17
“Design and Compilation” on page 28
“Verification” on page 45
“Design Debugging” on page 55
“Testing” on page 56
“Other Considerations” on page 56
Cyclone III Device Family Overview
®
III FPGA family offered by Altera
Cyclone III Design Guidelines
chapter in volume 1 of the Cyclone III
®
is a cost-optimized, memory-rich
®
II software features that you
Table 1
AN-466-1.2
shows

Related parts for EP3C55F484I7

EP3C55F484I7 Summary of contents

Page 1

... Company's (TSMC) 65-nm low-power (LP) process technology with additional silicon optimizations and software features to minimize power consumption. With this third generation in the Cyclone series, Altera broadens the number of high volume, cost-sensitive applications that can benefit from FPGAs. With a good design practice and a clear understanding of the design flow of the Cyclone III device, your design flow will be much easier ...

Page 2

... EP3C10 EP3C16 EP3C25 EP3C40 10,320 15,408 24,624 39,600 414 504 594 1,134 126 chapter in volume 1 of the Cyclone III Device Device Selection EP3C55 EP3C80 EP3C120 55,856 81,264 119,088 2,340 2,745 3,888 156 244 288 High-Speed © November 2008 Altera Corporation ...

Page 3

... Notes to Table 2: (1) For more information about the device packaging specifications, refer to the support section of the Altera website. (www.altera.com/support/devices/packaging/specifications/pkg-pin/spe-index.html). (2) The numbers are the maximum I/O counts (including clock input pins) supported by the device-package combination and can be affected by the configuration scheme selected for the device. ...

Page 4

... The power supply must be able to provide enough current for the device operation and the thermal solution must be able to cool the device junction temperature to within the specification. Altera provides a power estimation tool called the Early Power Estimator (EPE) to help you estimate the power consumption of your design during the system planning phase ...

Page 5

... If a voltage referenced input is not utilized for a V released automatically by the Quartus II software for use as an I/O pin but with higher pin capacitance due to the power bus loading effects. © November 2008 Altera Corporation Selection Criteria Performance of other I/O banks. Eight I/O banks are offered for ...

Page 6

... To obtain device pin-outs for Cyclone III devices, refer to the the Literature section of the Altera website (www.altera.com). Planning and Selecting Configuration Scheme Choose your device configuration method early to allow system and board designers to determine if any additional devices are required for your system ...

Page 7

... MSEL pin settings, refer to the Devices chapter in volume 1 of the Cyclone III Device Handbook. For the new user of Altera device configuration schemes, the available choice of configuration schemes and methods in which the configuration schemes can be set up may be overwhelming. In general, Altera configuration schemes are categorized into the following configuration schemes: ■ ...

Page 8

... For more information on the configuration scheme selection, refer to the Configuration that provide an overview of Altera FPGA configuration schemes and a general comparison of the schemes to guide you in choosing the one that best suits your design requirements. All configuration schemes use a configuration device, a download cable or an external ...

Page 9

... Configuration Devices You can use the Altera’s serial configuration devices (EPCS) in the AS configuration scheme. Supported commodity parallel flash families are used in the AP configuration scheme. Check whether the configuration device supports the configuration bitstream file size of your Cyclone III device. In the PS and FPP configuration schemes, you can use a MAX II device or a microprocessor with a flash memory configuration method ...

Page 10

... You can use the same download cable to program configuration devices on the board and use JTAG debugging tools such as the SignalTap f For more information about how to use Altera’s current download cables, refer to the following documents: ■ USB-Blaster Download Cable User Guide ■ ...

Page 11

... Quartus II software. You can implement remote update in conjunction with real-time decompression of configuration data if you must save configuration memory space in the serial configuration device with AS configuration. To implement the remote system upgrade interface, you can use the altremote_update megafunction. © November 2008 Altera Corporation Page 11 AN 478: Using FPGA-Based Table 4 on page 9 ...

Page 12

... PLL clock outputs can drive the dedicated clock output pin or global clock networks. chapter in volume 1 of the Cyclone III Device chapter in volume 1 of the Cyclone III Device Handbook. video applications, refer to Supporting Unknown F Early System Planning Remote Clock Networks and PLLs in Video Applications REF © November 2008 Altera Corporation ...

Page 13

... PLL according to your application. Selecting the Right Compensation Mode Table 5 shows the four compensation modes that Cyclone III devices support. © November 2008 Altera Corporation Cyclone III Device Datasheet: DC and Switching chapter in volume 2 of the Cyclone III Device Handbook Page 13 ...

Page 14

... Choose this mode if you want the external clock output pin to be phase-aligned with the clock input pin for zero delay through the device. chapter in volume 2 of the Cyclone III Device Description Early System Planning ) delays CO Cyclone III Device chapter in volume 2 of signal (t ). areset ARESET © November 2008 Altera Corporation ...

Page 15

... The SignalTap II Embedded Logic Analyzer requires JTAG connection and communicates with the device through an Altera download cable. Additional LEs and the M9K memory are needed as well. To minimize changes to your Cyclone III device's performance and reduce compilation time when you use the SignalTap II Embedded Logic Analyzer, back-annotate your design and use incremental compilation ...

Page 16

... JTAG megafunction gives you a greater level of control but at the cost of greater complexity. The feature needs the sld_virtual_jtag megafunction instantiated in your design before compilation and requires JTAG connection for the communication through an Altera download cable. Additional LEs are needed when this feature is used. f ...

Page 17

... Assignment Editor. The Output Enable Group assignment is another setting that is useful especially in external memory interfaces to allow efficient placement of output or bidirectional pins the group. © November 2008 Altera Corporation Cyclone III Device Datasheet: DC and in volume 2 of the Cyclone III Device Handbook. AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5 V ...

Page 18

... RESERVED_INPUT_WITH_BUS_HOLD pins can be left unconnected. to minimize V sag ground to minimize ground bounce. You can CC AN 224: High-Speed Board Layout Guidelines , ground, or another signal source can create CC Board Design Considerations I/O Management chapter in sag or ground bounce CC AN 508: Cyclone III and © November 2008 Altera Corporation ...

Page 19

... For the possible values of each power supply and the recommendation operation conditions, refer to the chapter in volume 2 of the Cyclone III Device Handbook. © November 2008 Altera Corporation AN 315: Guidelines for Designing High-Speed FPGA PCBs. www.altera.com when they are available. You can also use ...

Page 20

... If voltage reference I/O standards are not used in the bank, the VREF pins are available as user I/O pins In Cyclone III devices, Altera suggests that you use a linear regulator to power the V pins because they power the analog circuitry. You can power the digital voltage ...

Page 21

... Minimum CC Note to Figure 1: (1) V ramp must be monotonic. CC Requirements and Behavior The requirement and behavior of a Cyclone III device are detailed in stage prior to configuration. © November 2008 Altera Corporation Voltage V Ramp POR Time Configuration Time CC Time Page 21 chapter in volume 1 of the Time ...

Page 22

... POR trip point during user CCINT CCA chapter in volume 1 of the Cyclone III Device Handbook. Board Design Considerations Behavior Hot Socketing chapter in volume 1 of the Cyclone III to GND C C supplies CC Hot Socketing and Power-On © November 2008 Altera Corporation ...

Page 23

... JTAG/Configuration Pin Pull-up/Down Noise at the JTAG pins, whether the device is in ISP or user mode, or during power up, can cause the device to go into an undefined state or mode. Altera recommends pulling the TCK pin low and the TMS pin high through resistors. The JTAG circuitry is activated when V are connected to V floating ...

Page 24

... Notes to Table 9: (1) When interfacing the download cables with the Cyclone III device, you must ensure that all I/O inputs to the device maintain a maximum AC voltage of 4.1 V. Altera recommends powering up the download cables with V 3 your Cyclone III devices. (2) When using device V ...

Page 25

... The JTAG signal integrity determines the need to buffer a JTAG chain. Pay particular attention to the TCK signal because it is the JTAG clock and is the fastest switching signal compared to the other JTAG signals. Altera recommends buffering the signals at the connector because cables and board connectors tend to act as poor transmission lines and introduce noise to the signals ...

Page 26

... MSEL pins to V resistors. Alternatively, set up your board so that you can connect each pin to either V or GND with a 0- CCA testing or debugging. Altera recommends not to drive the MSEL pins with a microprocessor or another device not leave the MSEL pins floating. f For more information about configuration, refer to the chapter in volume 1 of the Cyclone III Device Handbook ...

Page 27

... I/O Bank 1 must be 3 you use the AP configuration scheme for Cyclone III devices, the V and must be either 1.8, 2.5, 3.0 or 3.3 V. Altera recommends not to use level shifters between a configuration device and the Cyclone III device in any active (AS or AP) configuration scheme. ...

Page 28

... Effective coding helps the synthesis tool to perform better when synthesizing your design. chapter in volume 1 of the Cyclone III Device ® Embedded Memory (P30 and P33) flash families. Configuring Cyclone III Devices chapter in © November 2008 Altera Corporation Design and Compilation ...

Page 29

... HDL as well. Selecting a Synthesis Tool The Quartus II software can synthesize design entries in Verilog HDL, VHDL, Altera hardware description language (AHDL) and schematics. You can also use third-party EDA synthesis tools to synthesize your Verilog or VHDL design, and then use the Quartus II software to perform the placement and routing based on the generated netlist ...

Page 30

... This is especially useful for system developers who are more familiar in the C/C++ programming language than the hardware description language. f For more information on the IP cores offered by Altera and its third-party IP partners, refer to the Altera website at www.altera.com/products/ip/ipm-index.html. Using Megafunctions Altera provides parameterizable megafunctions that are optimized for Altera device architectures ...

Page 31

... Synchronization eliminates the unwanted functional changes. f For more information about synchronizing your design, refer to the Recommendations for Altera Devices and the Quartus II Design Assistant volume 1 of the Quartus II Handbook or the Quartus II Help. © November 2008 Altera Corporation D ...

Page 32

... Figure 5. Registering the Input and Output Signals Clock Signal of Higher Frequency Clock Signal of Higher Frequency chapter in volume 1 of the Cyclone III (Figure 5) if you have a clock signal with a Input Signal Combinational Input Clock Generation Signal Circuitry Design and Compilation Generated Clock Signal © November 2008 Altera Corporation ...

Page 33

... Networks and PLLs in Cyclone III Devices Handbook. f For information about how to use the clock control block, refer to the Megafunction User Guide. © November 2008 Altera Corporation Clock Networks and PLLs in Cyclone III Devices altclkctrl Megafunction User Guide. chapter in volume 1 of the Cyclone III Device ...

Page 34

... Set the register in the Quartus II design to power up high before design compilation. In the Quartus II integrated synthesis, you can apply the Power-Up Level logic option in the Assignment Editor, with a Tcl assignment, or create an altera_attribute assignment in your source code. D ...

Page 35

... Design Assistant The Quartus II Design Assistant analyzes the reliability of a design based on Altera-recommended design guidelines or design rules during design compilation. The Design Assistant checks rules related to areas such as clocks, resets, timing closure, and non-synchronous design structure. You can select the areas you want the Design Assistant to check and the Design Assistant will report any design violation based on the settings you specified ...

Page 36

... When the design partitions are specified, you can use the Incremental Compilation Advisor to ensure that the partitions meet Altera's recommendations. Having the source code for each design block in a separate file allows you to make changes to the block separately ...

Page 37

... The Quartus II software offers power-driven compilation to reduce your design core dynamic power. Depending on the design, power-optimized synthesis and fitting can help reduce dynamic power by an average 16%. Altera recommends activating both the options to achieve minimal power consumption. However, you should prioritize your design timing constraint requirements over power optimization ...

Page 38

... Use lower voltage I/O CCIO around the reference voltage, so dynamic power is lower CCIO Design and Compilation altclkctrl © November 2008 Altera Corporation ...

Page 39

... While the Pin Planner provides an intuitive graphical representation of the targeted device, the Assignment Editor provides a spreadsheet-like interface that allows you to create and change all pin-related assignments. © November 2008 Altera Corporation groups, and differential pin pairings. The visual representation of REF Page 39 ...

Page 40

... For more details, refer to Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems large data bus is used in which pins may switch simultaneously, Altera recommends turning on the slew rate control to reduce simultaneous switching output (SSO) effects such as crosstalk and ground bounce. Slew rate control is only available in single-ended I/O standards with 8 mA current strength or higher ...

Page 41

... Cyclone III Device Handbook. Pin Assignment The following are the recommended pin assignments in the Quartus II software for the PLL input and output ports. © November 2008 Altera Corporation Cyclone III Device I/O Features chapter in volume 1 of chapter in volume 1 of the Cyclone III Device ...

Page 42

... Cyclone III devices support a CLKUSR f MAX clock, you can use user I/O pin. of 133 MHz. When you are not using the CLKUSR pin to supply external Design and Compilation Simulation © November 2008 Altera Corporation ...

Page 43

... Quartus II software supports data conversion into the following format: ■ Programmer Object File (.pof), ■ Hexadecimal (Intel-Format) Output File (.hexout), Raw Binary File (.rbf), ■ © November 2008 Altera Corporation pull-up resistor, indicating that reconfiguration can begin. Configuring Cyclone III Devices Page 43 . chapter in volume 1 of the ...

Page 44

... Software Settings section in volume 2 of the chapter in volume 3 of the Quartus II Handbook. I/O Management chapter in volume 2 of the Quartus II © November 2008 Altera Corporation Design and Compilation directly. The CC ...

Page 45

... The software also supports static timing analysis in the industry-standard Synopsys Primetime software. Specify the tool in the New Project Wizard or the EDA Tools Settings page of the Settings dialog box to generate the required timing netlist. © November 2008 Altera Corporation Cyclone III Device I/O Features chapter in volume 1 of the Cyclone III ...

Page 46

... Quartus II Quartus II TimeQuest Timing Analyzer chapters, respectively, in volume 3 of the Quartus II Handbook. Figure 8. Typically, the estimated delays are within 10% of those Verification Quartus II TimeQuest Timing and the Quartus II Classic © November 2008 Altera Corporation ...

Page 47

... November 2008 Altera Corporation , and t values from the timing report. For example can cause the register output to become metastable Quartus II TimeQuest Timing Analyzer chapters, respectively, in volume 3 of the Quartus II Handbook. Page 47 MAX SU CO and the Quartus II Classic AN 42: Metastability in Altera ...

Page 48

... Fitter attempts to meet the requirement. Area and Timing Optimization Physical synthesis optimizations make placement-specific changes to the netlist that improve results for a specific Altera device. You can specify Physical synthesis for performance or Physical synthesis for fitting options under the Fitter Settings Figure 9 ...

Page 49

... Quartus II software settings for your design. The Search for Best Performance and Search for Best Area options under Exploration Settings Figure 10, use a predefined exploration space to target design performance or area improvements with multiple compilations. © November 2008 Altera Corporation Netlist Optimizations and Physical Synthesis Page 49 chapter ...

Page 50

... Design Space Explorer chapter in volume 1 of the Quartus II Handbook and the chapter in volume 2 of the Quartus II Handbook. Figure 11. When this option is on, the design is optimized to meet its Verification chapter in volume 2 of the Quartus II Area and © November 2008 Altera Corporation ...

Page 51

... TimeQuest. This option directs the TimeQuest Timing Analyzer to analyze the design and generate slack reports for the slow and fast corners. Figure 12. TimeQuest Timing Analyzer Settings © November 2008 Altera Corporation Page 51 Figure 11, or ...

Page 52

... Help. The Quartus II Help shows the meaning of the message. f For more information about messages and message suppression, refer to the Quartus II Projects chapter in volume 3 of the Quartus II Handbook. chapter in volume 2 of the Quartus II Handbook. Verification Managing © November 2008 Altera Corporation ...

Page 53

... Compilation Process Settings page of the Settings dialog box Figure 13. The default value for the number of processors is 1, which disables parallel compilation. Figure 13. Specifying the Number of Processors © November 2008 Altera Corporation “Planning for Hierarchical and 35. “Planning for Hierarchical and Team-Based 35. Page 53 ...

Page 54

... Debugging your design at lower level saves you debugging time. You can monitor pins or registered signals through simulation. Area and Timing Optimization chapter in volume 3 of the Quartus II Handbook. chapter in volume 3 of the Quartus II Handbook. © November 2008 Altera Corporation Verification chapter in volume 2 of ...

Page 55

... You can perform simulation on your Cyclone III design using various simulation tools. Among the commonly used third-party simulation tools are the Mentor Graphics ModelSim ModelSim-Altera edition, ModelSim-Altera web edition as well as the Quartus II Simulator. Both ModelSim-Altera edition and ModelSim-Altera web edition support the Cyclone III family. ...

Page 56

... Tool Command Language (Tcl) script that uses the .pin file of the design generated by the Quartus II software and the BSDL file of the pre-configured device available from the Altera website to generate another BSDL file with modified port definitions and boundary-scan cell groups’ attributes. ...

Page 57

... Clock Networks and PLLs in Cyclone III Devices chapter in volume 1 of the Cyclone III ■ Device Handbook ■ Supporting Unknown FREF Video Applications with PLLs white paper ■ Cyclone III Device Datasheet: DC and Switching Characteristics chapter in volume 2 of the Cyclone III Device Handbook © November 2008 Altera Corporation Page 57 ...

Page 58

... Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook ■ Synthesis in volume 1 of the Quartus II Handbook Volume 4: SOPC Builder of the Quartus II Handbook ■ Design Recommendations for Altera Devices and the Quartus II Design Assistant ■ chapter in volume 1 of the Quartus II Handbook ■ altclkctrl Megafunction User Guide ■ ...

Page 59

... Quartus II Programmer chapter in volume 3 of the Quartus II Handbook ■ Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook ■ Synopsys PrimeTime Support chapter in volume 3 of the Quartus II Handbook AN 42: Metastability in Altera Devices ■ ■ Netlist Optimizations and Physical Synthesis chapter in volume 2 of the Quartus II Handbook ■ ...

Page 60

... Synthesis Tool” section. “Using Megafunctions” section. “Planning for Hierarchical and Team-Based section. “Verification” section. Table 1 Table 7. Table 4. Figure 8, Figure 9, Figure 10, Figure and Figure 13. Document Revision History Summary of Changes — — 11, — © November 2008 Altera Corporation ...

Page 61

... Select the PLL compensation mode that best fits your design requirement. 18 Use the PLL reconfiguration feature, if you need to change the PLL settings on the fly in user mode without reconfiguring the entire Cyclone III device. © November 2008 Altera Corporation and V in the same I/O bank. CCIO ...

Page 62

... If you are using HDL for design entry, use the recommended coding styles control signals as required by your design. locked pfdena or ground C C DCLK or TCK signals are clean. pins unconnected. JTAG pins ground directly based on the configuration scheme used. MSEL CC A Design Checklist © November 2008 Altera Corporation ...

Page 63

... Assign the ports of the altpll megafunction and the altpll_reconfig megafunction to the recommended pins. 65 Perform timing or functional simulation on your PLL design to check the functionality. 66 Use the CLKUSR © November 2008 Altera Corporation pin to control the initialization upon the completion of the configuration. Page 63 ...

Page 64

... command for multicycle path timing analysis. constraint to create generated clocks for PLLs. constraint to apply inter-clock, intra-clock, and constraint to generate a report on any problem with the design Design Checklist , or f violation. MAX © November 2008 Altera Corporation ...

Page 65

... Use the BSDLCustomizer tool to regenerate the BSDL file based on your design. “Other Considerations” on page 56 Done N cautious of ESD when handling the device. 97 Operate the device within the recommended operating conditions. 98 Use the Cyclone III FPGA Starter Kit to test out various features of the Cyclone III device. © November 2008 Altera Corporation Page 65 ...

Page 66

... Page 66 © November 2008 Altera Corporation ...

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