EP1SGX10DF672C6N Altera, EP1SGX10DF672C6N Datasheet - Page 24
EP1SGX10DF672C6N
Manufacturer Part Number
EP1SGX10DF672C6N
Description
IC STRATIX GX FPGA 10KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX10DF672C6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
362
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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2–14
Stratix GX Device Handbook, Volume 1
Figure 2–10
■
■
Figure 2–10. Receiver Input Buffer
Programmable Termination
The programmable termination can be statically set in the Quartus II
software.
termination.
Figure 2–11. Programmable Receiver Termination
If you use external termination, then the receiver must be externally
terminated and biased to 1.1 V.
external termination/biasing circuit.
Input
Pins
Programmable termination
Programmable equalizer
Figure 2–11
Programmable
shows a diagram of the receiver input buffer, which contains:
Termination
50, 60, or 75 Ω
50, 60, or 75 Ω
shows the setup for programmable receiver
Programmable
Figure 2–12
Equalizer
V
CM
shows an example of an
Differential
Altera Corporation
Buffer
Input
Differential
June 2006
Buffer
Input
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