EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 125
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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Chapter 5: Clock Networks and PLLs in Arria II GX Devices
PLLs in Arria II GX Devices
© July 2010
Altera Corporation
When the rbypass bit is set to 1, it bypasses the counter, resulting in a divide by 1.
When this bit is set to 0, the high- and low-time counters are added to compute the
effective division of the VCO output frequency. For example, if the post-scale divide
factor is 10, the high- and low-count values could be set to 5 and 5, respectively, to
achieve a 50-50% duty cycle. The PLL implements this duty cycle by transitioning the
output clock from high to low on the rising edge of the VCO output clock. However, a
4 and 6 setting for the high- and low-count values, respectively, would produce an
output clock with a 40-60% duty cycle.
The rselodd bit indicates an odd divide factor for the VCO output frequency along
with a 50% duty cycle. For example, if the post-scale divide factor is 3, the high- and
low-time count values could be set to 2 and 1, respectively, to achieve this division.
This implies a 67%-33% duty cycle. If you require a 50%-50% duty cycle, you can set
the rselodd control bit to 1 to achieve this duty cycle despite an odd division factor.
The PLL implements this duty cycle by transitioning the output clock from high to
low on a falling edge of the VCO output clock. When you set rselodd = 1, you
subtract 0.5 cycles from the high time and you add 0.5 cycles to the low time. For
example:
■
■
■
Scan Chain Description
Arria II GX PLLs have a 180-bit scan chain.
component of an Arria II GX PLL.
Table 5–10. Arria II GX PLL Reprogramming Bits (Part 1 of 2)
C6
C5
C4
C3
C2
C1
C0
M
N
Charge Pump Current
VCO Post-Scale divider (K)
Loop Filter Capacitor
High-time count = 2 cycles
Low-time count = 1 cycle
rselodd = 1 effectively equals:
■
■
■
(2)
High-time count = 1.5 cycles
Low-time count = 1.5 cycles
Duty cycle = (1.5/3) % high-time count and (1.5/3) % low-time count
Block Name
(3)
Counter
Table 5–10
16
16
16
16
16
16
16
16
16
0
1
0
Number of Bits
lists the number of bits for each
Arria II GX Device Handbook, Volume 1
Other
2
2
2
2
2
2
2
2
2
3
0
2
(1)
Total
18
18
18
18
18
18
18
18
18
3
1
2
5–33
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