EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 275

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Design Security
ALTREMOTE_UPDATE Megafunction
Figure 9–28. Interface Signals between the ALTREMOTE_UPDATE Megafunction and the Nios II Processor
Design Security
© July 2010
Altera Corporation
f
Use the ALTREMOTE_UPDATE megafunction option in the Quartus II software to
the interface between the remote system upgrade circuitry and the device logic array
interface. Using the megafunction block instead of creating your own logic saves
design time and offers more efficient logic synthesis and device implementation.
The ALTREMOTE_UPDATE megafunction provides a memory-like interface to the
remote system upgrade circuitry and handles the shift register read and write
protocol in the Arria II GX device logic. This implementation is suitable for designs
that implement the factory configuration functions using a Nios II processor or user
logic in the device.
Figure 9–28
megafunction and Nios II processor or user logic.
For more information about the ALTREMOTE_UPDATE megafunction and the
description of ports listed in
(ALTREMOTE_UPDATE) Megafunction User
This section provides an overview of the design security features and their
implementation on Arria II GX devices using advanced encryption standard (AES). It
also describes the security modes available in Arria II GX devices that allow you to
use these new features in your designs.
As Arria II GX devices continue to play roles in larger and more critical designs in
competitive commercial and military environments, it is increasingly important to
protect your designs from copying, reverse engineering, and tampering.
Nios II Processor or
User Logic
shows the interface signals between the ALTREMOTE_UPDATE
Figure
9–28, refer to the
read_param
write_param
param[2..0]
data_in[23..0]
reconfig
reset_timer
clock
reset
busy
data_out[23..0]
Guide.
ALTREMOTE_UPDATE
Remote Update Circuitry
Arria II GX Device Handbook, Volume 1
9–55