EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 32

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–6
Figure 2–6. Arria II GX ALM Connection Details
Arria II GX Device Handbook, Volume 1
datac0
datac1
dataf0
datae0
dataa
datab
datae1
dataf1
Figure 2–6
The clock and clear control signals of an ALM’s register can be driven by global
signals, general-purpose I/O pins, or any internal logic. General-purpose I/O pins or
internal logic can drive the clock enable. For combinational functions, the register is
bypassed and the output of the look-up table (LUT) drives directly to the outputs of
an ALM.
Each ALM has two sets of outputs that drive the local, row, and column routing
resources. The LUT, adder, or register output can drive these outputs (refer to
Figure
or direct link routing connections, and one of these ALM outputs can also drive local
interconnect resources. This allows the LUT or adder to drive one output while the
register drives another output.
3-INPUT
3-INPUT
3-INPUT
3-INPUT
4-INPUT
4-INPUT
2–6). For each set of output drivers, two ALM outputs can drive column, row,
LUT
LUT
LUT
LUT
LUT
LUT
shared_arith_out
shared_arith_in
shows a detailed view of all the connections in an ALM.
carry_in
carry_out
+
+
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices
V CC
GND
clk[2:0]
syncload
sclr
aclr[1:0]
reg_chain_in
© June 2009 Altera Corporation
D
D
CLR
CLR
reg_chain_out
Q
Q
Adaptive Logic Modules
local
interconnect
row, column
direct link routing
row, column
direct link routing
local
interconnect
row, column
direct link routing
row, column
direct link routing