EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 135

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Figure 5–25. Phase Relationship Between PLL Clocks in Zero Delay Buffer Mode for Arria II Devices
Note to
(1) The internal PLL clock output can lead or lag the external PLL clock outputs.
December 2010 Altera Corporation
Figure
5–25:
Figure 5–25
ZDB mode.
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port
Dedicated PLL
Clock Outputs (1)
External Feedback Mode
In external feedback mode, the external feedback input pin (fbin) is phase-aligned
with the clock input pin, as shown in
remove clock delay and skew between devices. This mode is supported on all
Arria II GZ PLLs.
In external feedback mode, the output of the M counter (FBOUT) feeds back to the PLL
fbin input (using a trace on the board) becoming part of the feedback loop. Also, use
one of the dual-purpose external clock outputs as the fbin input pin in this mode.
You must use the same I/O standard on the input clock, feedback input, and output
clocks. Left and right PLLs support this mode when using single-ended I/O
standards only.
shows an example waveform of the PLL clocks’ phase relationship in
Phase Aligned
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Figure
5–26. Aligning these clocks allows you to
5–31