EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 142
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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5–38
Figure 5–31. Automatic Switchover Upon Loss of Clock Detection for Arria II Devices
Note to
(1) Switchover is enabled on the falling edge of inclk0 or inclk1, depending on which clock is available. In this figure, switchover is enabled on
Arria II Device Handbook Volume 1: Device Interfaces and Integration
the falling edge of inclk1.
Figure
5–31:
When you use automatic switchover mode, the clkbad[0] and clkbad[1] signals
indicate the status of the two clock inputs. When they are asserted, the clock sense
block has detected that the corresponding clock input has stopped toggling. These
two signals are not valid if the frequency difference between inclk0 and inclk1 is
greater than 20%.
The activeclock signal indicates which of the two clock inputs (inclk0 or inclk1) is
being selected as the reference clock to the PLL. When the frequency difference
between the two clock inputs is more than 20%, the activeclock signal is the only
valid status signal.
Figure 5–31
switchover mode. In this example, the inclk0 signal is stuck low. After the inclk0
signal is stuck at low for approximately two clock cycles, the clock sense circuitry
drives the clkbad[0] signal high. Also, because the reference clock signal is not
toggling, the switchover state machine controls the multiplexer through the clksw
signal to switch to the backup clock, inclk1.
Manual Override Mode
In automatic switchover with manual override mode, you can use the clkswitch
input for user- or system-controlled switch conditions. You can use this mode for
same-frequency switchover or to switch between inputs of different frequencies. For
example, if inclk0 is 66 MHz and inclk1 is 200 MHz, you must control the
switchover when you use clkswitch because the automatic clock-sense circuitry
cannot monitor clock input (inclk0 and inclk1) frequencies with a frequency
difference of more than 100% (2×). This feature is useful when the clock sources
originate from multiple cards on the backplane, requiring a system-controlled
activeclock
clkbad0
clkbad1
muxout
inclk0
inclk1
shows an example waveform of the switchover feature with automatic
(1)
Chapter 5: Clock Networks and PLLs in Arria II Devices
December 2010 Altera Corporation
PLLs in Arria II Devices
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