EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 153
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Table 5–20. PLL Counter Settings for Arria II Devices
Table 5–21. Dynamic Phase-Shifting Control Signals for Arria II Devices (Part 1 of 2)
December 2010 Altera Corporation
Notes to
(1) For Arria II GX devices.
(2) For Arria II GZ devices
(3) Counter-bypass bit.
PHASECOUNTERSELECT[3:0]
PHASEUPDOWN
PHASESTEP
0 (1), X
LSB
X
Table
(2)
Signal Name
5–20:
f
1
X
X
Bypassing PLL
Bypassing a PLL counter results in a multiply (m counter) or a divide (n and C0 to C9
counters) factor of one.
Table 5–20
For more information about how to use the PLL scan chain bit settings, refer to the
Phase Locked-Loops Reconfiguration (ALTPLL_RECONFIG) Megafunction User
To bypass any of the PLL counters, set the bypass bit to 1, causing the values on the
other bits to be ignored. To bypass the VCO post-scale counter (K), set the
corresponding bit to 0.
Dynamic Phase-Shifting
The dynamic phase-shifting feature allows the output phases of individual PLL
outputs to be dynamically adjusted relative to each other and to the reference clock
without having to send serial data through the scan chain of the corresponding PLL.
This feature simplifies the interface and allows you to quickly adjust clock-to-out (t
delays by changing the output clock phase-shift in real time. This adjustment is
achieved by incrementing or decrementing the VCO phase-tap selection to a given
C counter or to the M counter. The phase is shifted by 1/8 of the VCO frequency at a
time. The output clocks are active during this phase-reconfiguration process.
Table 5–21
X
X
X
X
Counter select. Four bits decoded to select
either the M or one of the C counters for phase
adjustment. One address maps to select all
C counters. This signal is registered in the PLL
on the rising edge of scanclk.
Selects dynamic phase shift direction;
1 = UP; 0 = DOWN. Signal is registered in the
PLL on the rising edge of scanclk.
Logic high enables dynamic phase shifting.
lists the settings for bypassing the counters in Arria II PLLs.
lists the control signals that are used for dynamic phase-shifting.
X
X
X
X
PLL Scan Chain Bits [0..8] Settings
X
X
Description
X
X
1
0
MSB
Arria II Device Handbook Volume 1: Device Interfaces and Integration
(3)
(3)
PLL counter bypassed
PLL counter not bypassed because bit 8 (MSB) is set to 0
Logic array or
I/O pins
Logic array or
I/O pin
Logic array or
I/O pin
Source
Description
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
Destination
Guide.
5–49
CO
)
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