EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 195

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6: I/O Features in Arria II Devices
Design Considerations
December 2010 Altera Corporation
I/O Placement Guidelines
Pin Placement Guideline
This section provides I/O placement guidelines for the programmable I/O standards
supported by Arria II devices and includes essential information for designing
systems with an Arria II device’s selectable I/O capabilities.
3.3-V, 3.0-V, and 2.5-V LVTTL/LVCMOS Tolerance Guidelines
Altera recommends the following techniques when you use 3.3-, 3.0-, and 2.5-V I/O
standards to limit overshoot and undershoot at I/O pins:
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Altera recommends creating a Quartus II design, enter your device I/O assignments,
and compile your design to validate your pin placement. The Quartus II software
checks your pin connections with respect to I/O assignment and placement rules to
ensure proper device operation. These rules are dependent on device density,
package, I/O assignments, voltage assignments, and other factors that are not
described in this chapter.
Low drive strength or series termination—the impedance of the I/O driver must
be equal to or greater than the board trace impedance to minimize overshoot and
undershoot at the un-terminated receiver end. If high driver strength (lower driver
impedance) is required, Altera recommends series termination at the driver end
(on-chip or off-chip).
Output slew rate—Arria II GX devices have two levels and Arria II GZ devices
have four levels of slew rate control for single-ended output buffers. Slow slew
rate can significantly reduce the overshoot and undershoot in the system at the
cost of slightly slower performance.
Input clamping diodes—Arria II I/Os have on-chip clamping diodes. These
clamping diodes are required for PCI/PCI-X standards, and recommended for
3.3-V LVTTL/CMOS standards.
When you use clamping diodes, the floating well of the I/O is clamped to V
As a result, the Arria II device might draw extra input leakage current from the
external input driver. This may violate the hot-socket DC- and AC-current
specification and increase power consumption. With the clamping diode enabled,
the Arria II device supports a maximum DC current of 8 mA.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
CCIO
6–37
.