EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 211

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Arria II Devices
Memory Interfaces Pin Support for Arria II Devices
Figure 7–12. Number of DQ/DQS Groups per Bank in EP2AGZ225 Devices in the 1152-Pin FineLine BGA Package
Notes to
(1) These numbers are preliminary until the devices are available.
(2) EP2AGZ225 devices do not support the ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R
(4) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(5) You can also use some of the DQ/DQS pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQ/DQS group with any of its pin members
December 2010 Altera Corporation
(2), (3), (4),
DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface” on page
of the ×4 group are used as R
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
used for configuration purposes. Ensure that the DQ/DQS groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQ/DQS groups, depending on your configuration scheme.
Figure
48 User I/Os
(5)
42 User I/Os
I/O Bank 1C
I/O Bank 1A
×16/×18=1
×16/×18=1
7–12:
×8/×9=3
×8/×9=3
DLL1
×4=7
×4=6
DLL0
Figure 7–12
EP2AGZ225 devices in the 1152-pin FineLine BGA package.
I/O Bank 8A
40 User I/Os
40 User I/Os
I/O Bank 3A
×16/×18=1
×16/×18=1
×8/×9=3
×8/×9=3
UP
×4=6
×4=6
and R
DN
shows the number of DQ/DQS groups per bank in Arria II GZ
pins for OCT calibration. If two pins of a ×4 group are used as R
24 User I/Os 32 User I/Os
I/O Bank 3B
24 User I/Os 32 User I/Os 32 User I/Os
I/O Bank 8B
×16/×18=1
×16/×18=1
×8/×9=2
×8/×9=2
×4=4
×4=4
I/O Bank 3C
in the 1152-Pin FineLine BGA
I/O Bank 8C I/O Bank 7C
×16/×18=0
×16/×18=0
×8/×9=1
×8/×9=1
×4=3
×4=3
EP2AGZ225 Devices
UP
and R
7–21.
32 User I/Os
I/O Bank 4C
×16/×18=0
×16/×18=0
DN
×8/×9=1
×8/×9=1
pins, but you cannot use a ×4 group for memory interfaces if two pins
×4=3
×4=3
Arria II Device Handbook Volume 1: Device Interfaces and Integration
I/O Bank 4B
24 User I/Os 40 User I/Os
I/O Bank 7B
24 User I/Os 40 User I/Os
×16/×18=1
×16/×18=1
×8/×9=2
×8/×9=2
×4=4
×4=4
I/O Bank 4A
×16/×18=1
I/O Bank 7A
×16/×18=1
×8/×9=3
×8/×9=3
UP
×4=6
×4=6
and R
DN
pins for OCT calibration, you
48 User I/Os
42 User I/Os
I/O Bank 6C
I/O Bank 6A
×16/×18=1
×16/×18=1
×8/×9=3
×8/×9=3
“Combining ×16/×18
DLL2
DLL3
×4=7
×4=6
(Note
7–15
1),