EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 24

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–10
Arria II Device Handbook Volume 1: Device Interfaces and Integration
DSP Resources
I/O Features
Table 1–6
Table 1–6. Memory Modes for Arria II Devices
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Table 1–7. I/O Standards Support for Arria II Devices
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Single Port
Simple Dual Port
True Dual Port
Single-Ended I/O
Differential I/O
Note to
(1) BLVDS is only available for Arria II GX devices.
Fulfills the DSP requirements of 3G and Long Term Evolution (LTE) wireless
infrastructure applications, video processing applications, and voice processing
applications
DSP block input registers efficiently implement shift registers for finite impulse
response (FIR) filter applications
The Quartus II software includes megafunctions you can use to control the mode
of operation of the DSP blocks based on user-parameter settings
You can directly infer multipliers from the VHDL or Verilog HDL source code
Contains up to 20 modular I/O banks
All I/O banks support a wide range of single-ended and differential I/O
standards listed in
Supports programmable bus hold, programmable weak pull-up resistors, and
programmable slew rate control
For Arria II devices, calibrates OCT or driver impedance matching for
single-ended I/O standards with one OCT calibration block on the I/O banks
listed in
Port Mode
Table
Type
lists the Arria II device memory modes.
1–7:
Table
1–8.
×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, ×36, ×64, and ×72
×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, ×36, ×64, and ×72
×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
LVTTL, LVCMOS, SSTL, HSTL, PCIe, and PCI-X
SSTL, HSTL, LVPECL, LVDS, mini-LVDS, Bus LVDS (BLVDS) (1), and
RSDS
Table
1–7.
Port Width Configuration
I/O Standard
Chapter 1: Overview for the Arria II Device Family
December 2010 Altera Corporation
Arria II Device Architecture