EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 408

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–22
Arria II Device Handbook Volume 2: Transceivers
Receiver Input Buffer
The receiver input buffer receives serial data from the rx_datain port and feeds it to
the CDR unit.
Figure 1–24. Receiver Input Buffer
Note to
(1) For more information about reverse serial pre-CDR loopback mode, refer to
Table 1–6
Table 1–6. Electrical Features Supported by the Receiver Input Buffer for Arria II
Devices
The following sections describe the features supported in the Arria II GX and GZ
receiver input buffers.
Programmable Differential OCT
The Arria II GX and GZ receiver input buffers support optional differential OCT of
85  (Arria II GZ only) or 100 
compensate for temperature, voltage, and process changes (for more information,
refer to
Assignment Editor by setting the assignment input termination to OCT 100  on the
receiver input buffer.
From Serial Data
Note to
(1) The differential OCT setting for Arria II GX and GZ transmitters and receivers is 85 (Arria II GZ only) or 100  .
(rx_datain)
Input Pins
I/O Standard
1.4 V PCML
1.5 V PCML
2.5 V PCML
Figure
LVPECL
Table
LVDS
“Calibration Block” on page
(Note 1)
lists the electrical features supported by the receiver input buffer.
1–24:
1–6:
Figure 1–24
Receiver Input Buffer
100 W
V
RX
CM
Programmable Common Mode Voltage (V)
0.82/1.1 V
shows the receiver input buffer.

. The resistance is adjusted in the calibration block to
1–47). You can set this option in the Quartus II
Equalization
Threshold
Detection
0.82
0.82
0.82
0.82
DC Gain
Circuitry
Circuitry
1.1
Signal
and
Chapter 1: Transceiver Architecture in Arria II Devices
“Test Modes” on page
the Reverse Serial Pre-CDR Loopback
To CDR
December 2010 Altera Corporation
To the Transmitter Output Buffer in
Signal
Detect
Configuration (1)
Receiver Channel Datapath
Coupling
AC, DC
AC, DC
AC, DC
1–85.
AC
AC