EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 424
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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1–38
Table 1–12. Word Aligner Options Available in Basic Single-Width and Double-Width Modes for Arria II
Devices
Arria II Device Handbook Volume 2: Transceivers
Basic
Single-Width
Functional
Mode
(Note 1)
PMA-PCS
(Part 1 of 2)
Interface
Width
10-bit
8-bit
Table 1–12
double-width modes.
Word Alignment
Synchronization
State Machine
Alignment
Alignment
Automatic
Manual
Bit-Slip
Manual
Bit-Slip
summarizes the word aligner options available in Basic single-width and
Mode
7- and 10-bit
7- and 10-bit
7- and 10-bit
Alignment
Pattern
Length
16-bit
16-bit
Word
rx_enapatternalign
Level Sensitive
Rising Edge
Sensitivity
Sensitive
—
—
—
Chapter 1: Transceiver Architecture in Arria II Devices
one parallel clock
one parallel clock
Asserted high for
Asserted high for
synchronization
word boundary.
word boundary.
aligns to a new
aligns to a new
rx_syncstatus
cycle when the
cycle when the
conditions are
Stays high as
word aligner
word aligner
long as the
Behavior
satisfied.
December 2010 Altera Corporation
—
—
Receiver Channel Datapath
pattern appears in
pattern appears in
pattern appears in
pattern appears in
pattern appears in
rx_patterndetect
Asserted high for
one parallel clock
Asserted high for
one parallel clock
Asserted high for
one parallel clock
Asserted high for
one parallel clock
Asserted high for
one parallel clock
the current word
the current word
the current word
the current word
the current word
word alignment
word alignment
word alignment
word alignment
word alignment
cycle when the
cycle when the
cycle when the
cycle when the
cycle when the
boundary.
boundary.
boundary.
boundary.
boundary.
Behavior
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