EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 494
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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2–4
Arria II Device Handbook Volume 2: Transceivers
Table 2–1
on the refclk pins.
Table 2–1. Electrical Specifications for the Input Reference Clock for Arria II Devices
Figure 2–3
configured as HCSL.
Figure 2–3. Termination Scheme for a Reference Clock Signal When Configured as HCSL
Notes to
(1) No biasing is required if the reference clock signals are generated from a clock source that conforms to the PCIe
(2) Select resistor values as recommended by the PCIe clock source vendor.
■
■
■
■
■
■
Notes to
(1) In PCI Express
(2) For an example termination scheme, refer to
(Note 1)
PCI Express (PIPE)
GIGE
XAUI
Serial RapidIO
SONET/SDH
SDI
Basic
specification.
if compliance to the PCIe protocol is required. The Quartus
external termination for the refclk pins signal if configured as HCSL.
Protocol
Figure
(1),
Table
lists the electrical specifications for the input reference clock signal driven
shows an example termination scheme for a reference clock signal when
(2)
2–1:
2–3:
REFCLK
(HCSL)
Source
PCIe
®
®
(PIPE) (PCIe) mode, you have the option of selecting the HCSL standard for the reference clock
■
■
■
■
■
■
■
■
■
■
1.2-V PCML
1.5-V PCML
2.5-V PCML
Differential LVPECL
LVDS
1.2-V PCML
1.5-V PCML
2.5-V PCML
DIfferential LVPECL
LVDS
I/O Standard
HCSL
Rp
Rs
Rs
=
(2)
(2)
50 Ω
Figure
2–3.
®
CMU PLL and Receiver CDR Input Reference Clocking
Chapter 2: Transceiver Clocking in Arria II Devices
II software automatically selects DC coupling with
Rp
Coupling
=
DC
AC
AC
50 Ω
December 2010 Altera Corporation
REFCLK
REFCLK
Arria II
Termination
+
-
Off-chip
On-chip
On-chip
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