EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 527

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
December 2010 Altera Corporation
Because all 16 channels are identical, using a single tx_clkout to clock the transmitter
phase compensation FIFO in all 16 channels results in only one global or regional
clock resource being used instead of four. To implement this clocking scheme, you
must choose the transmitter phase compensation FIFO write clocks instead of the
Quartus II software automatic selection, as described in
Phase Compensation FIFO Write
User-Selected Transmitter Phase Compensation FIFO Write Clock
The ALTGX MegaWizard Plug-In Manager provides an optional tx_coreclk port for
each instantiated transmitter channel. If you enable this port, the Quartus II software
does not automatically select the transmitter phase compensation FIFO write clock
source. Instead, the signal that you drive on the tx_coreclk port of the channel clocks
the write side of its transmitter phase compensation FIFO.
Use the flexibility of selecting the transmitter phase compensation FIFO write clock to
reduce clock resource utilization (global, regional, or both). You can connect the
tx_coreclk ports of all identical channels in your design and drive them using a
common clock driver that has 0 PPM frequency difference with respect to the FIFO
read clocks of all your channels. Use the common clock driver to clock the transmitter
data and control logic in the FPGA fabric for all identical channels. This FPGA
fabric-transceiver interface clocking scheme uses only one global or regional clock
resource for all identical channels in your design.
Clock”.
Arria II Device Handbook Volume 2: Transceivers
“User-Selected Transmitter
2–37