EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 531

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
Figure 2–23. Sixteen Identical Channels Across Four Transceiver Blocks for Example 5
Table 2–12. Quartus II Assignments for Arria II Devices
December 2010 Altera Corporation
From
To
Assignment Name
Value
Note to
(1) This is an example design hierarchy path for the tx_clkout[4] signal.
Assignment
Table
2–12:
Transceiver Block GXBL3
Transceiver Block GXBL2
Transceiver Block GXBL1
Transceiver Block GXBL0
Table 2–12
scheme shown in
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
top_level/top_xcvr_instance1/altgx_component/tx_clkout[4]
tx_dataout[15..0]
ON
GXB 0 PPM Core Clock Setting
Figure 2–23
transceiver blocks. The tx_coreclk ports of all 16 transmitter channels are
connected together and driven by the tx_clkout[4] signal from channel 0 in
transceiver block GXBL1. The tx_clkout[4] signal also drives the transmitter data
and control logic of all 16 transmitter channels in the FPGA fabric. Only one global
clock resource is used by the tx_clkout[4] signal with this clocking scheme.
Example 5: Sixteen Identical Channels Across Four Transceiver Blocks
lists the Quartus II assignments that you must make for the clocking
shows 16 identical transmitter channels located across four
tx_clkout[15:12]
tx_clkout[11:8]
tx_clkout[7:4]
tx_clkout[3:0]
Figure
2–23.
tx_coreclk[15:12]
tx_coreclk[11:8]
tx_coreclk[7:4]
tx_coreclk[3:0]
Description
tx_clkout[4]
FPGA Fabric
Arria II Device Handbook Volume 2: Transceivers
Channel [15:12]
Channel [11:8]
Channel [3:0]
Channel [7:4]
and Control
and Control
and Control
and Control
TX Data
TX Data
TX Data
TX Data
Logic
Logic
Logic
Logic
(1)
2–41