EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 557
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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Chapter 2: Transceiver Clocking in Arria II Devices
Document Revision History
Document Revision History
Table 2–17. Document Revision History
December 2010 Altera Corporation
December 2010
July 2010
November 2009
February 2009
Date
Table 2–17
Version
3.0
2.0
1.1
1.0
lists the revision history for this chapter.
■
■
■
■
■
■
■
■
■
■
Initial release.
Updated to add Arria II GZ information.
Removed “QL” designations.
Minor text edits.
Updated Figure 2–29.
Updated Table 2–2, Table 2–3, and Table 2–4.
Updated the “Non-Bonded Channel Configurations”, “Non-Bonded Receiver
Clocking without Rate Matcher”, and “Dedicated Left PLL Cascade Lines
Network” sections.
“(QLn)” (where n = 1 or 2) was added to all “GXBn” references.
Minor text edits.
Updated figures in the document for clarity.
Added “Using the CMU PLL for Clocking User Logic in the FPGA Fabric” on
page 2–64.
Changes
Arria II Device Handbook Volume 2: Transceivers
2–67
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