EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 570

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–12
Table 3–7. PCIe Hard IP Block Restrictions When Combining Transceiver Channels with Different Functional and/or
Protocol Modes for Arria II Devices
Combining Transceiver Instances Using PLL Cascade Clocks
Arria II Device Handbook Volume 2: Transceivers
PCI Express Configuration (PCI Express hard IP
Notes to
(1) Avail.—the channels can be used in other configurations.
(2) N/A—the channels are NOT available for use.
(3) Transceiver block 0—the master transceiver block that provides high-speed serial and low-speed parallel clocks in a PCIe ×4 or ×8
(4) Transceiver block 1—the adjacent transceiver block that shares the same PCIe hard IP block with transceiver block 0.
(5) The physical channel 0 in the transceiver block. For more information about physical-to-logical channel mapping in PCIe functional mode, refer
Options Enabled in the PCIe Compiler Wizard)
Width
Link
1
4
8
configuration.
to the “×8 Channel Configuration” section in the
Table
Combining Channels Using the PCIe hard IP Block with Other Channels
Interface Width)
3–7:
f
Lane (Data
128 bit
64 bit
64 bit
The Arria II device family contains an embedded PCIe hard IP block that performs the
physical, datalink, and transaction layer functionality specified by PCIe base
specification 1.1. Each PCIe hard IP block is shared by two transceiver blocks. The
PCIe Compiler MegaWizard Plug-In Manager provides you the options to configure
the PCIe hard IP block. When enabled, the transceiver channels associated with this
block are enabled.
There are restrictions on combining transceiver channels with different functional
and/or protocol modes (for example, Basic mode) within two contiguous transceiver
blocks with the channels that use the PCIe hard IP block. The restrictions depend on
the number of channels used (×1 or ×4) and the number of virtual channels (VC)
selected in the PCIe Compiler MegaWizard Plug-In Manager.
restrictions.
For more information about the PCIe Compiler MegaCore Functions and hard IP
implementation, refer to the
The Arria II device family provides multiple input reference clock sources to clock the
CMU PLLs and RX CDRs in each transceiver block. The following are the input
reference clock sources that can clock the CMU PLLs and RX CDRs:
■
■
■
■
refclks from the same transceiver block
Global clock lines
refclks from transceiver blocks on the same side of the device using the
inter-transceiver block (ITB) lines
PLL cascade clock (this is the cascaded clock output from the PLLs in the FPGA
fabric)
Channel (VC)
(Note
Virtual
1
1
1
1),
Arria II Transceiver Clocking
(2)
Ch0
PCIe ×1
PCIe ×4
PCIe ×8
Transceiver Block 0
(5)
Chapter 3: Configuring Multiple Protocols and Data Rates in Arria II Devices
PCI Express Compiler User
Avail.
Ch1
N/A
N/A
chapter.
Avail. Avail.
Ch2
N/A
N/A
Combining Transceiver Instances Using PLL Cascade Clocks
(3)
Ch3
N/A
N/A
Guide.
Avail.
Avail.
CH4
N/A
Transceiver Block 1
December 2010 Altera Corporation
Table 3–7
Avail.
Avail.
Ch5
N/A
Avail.
Avail.
lists the
Ch6
N/A
(4)
Avail.
Avail.
Ch7
N/A