EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 579
EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
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Chapter 4: Reset Control and Power Down in Arria II Devices
Transceiver Reset Sequences
Figure 4–2. Transceiver Reset Sequences Chart
Note to
(1) Refer to the Timing Diagram in
(2) Refer to the Timing Diagram in
(3) Refer to the Timing Diagram in
(4) Refer to the Timing Diagram in
(5) Refer to the Timing Diagram in
(6) Refer to the Timing Diagram in
(7) Refer to the Timing Diagram in
(8) Refer to the Timing Diagram in
December 2010 Altera Corporation
"Transmitter Only"
Figure
Channel (2)
4–2:
1
1
Bonded
Receiver CDR
Lock Mode (3)
in Automatic
The busy signal remains low for the first reconfig_clk clock cycle. It is then asserted
from the second reconfig_clk clock cycle. Subsequent de-assertion of the busy signal
indicates the completion of the offset cancellation process. This busy signal is
required in transceiver reset sequences except for Transmitter Only channel
configurations. Refer to the reset sequences shown in
references listed in the notes.
Altera strongly recommends adhering to these reset sequences for proper operation of
the Arria II transceiver.
Transmitter" Channel
"Receiver and
Figure 4–10 on page
Figure 4–3 on page
Figure 4–4 on page
Figure 4–5 on page
Figure 4–6 on page
Figure 4–7 on page
Figure 4–8 on page
Figure 4–9 on page
Receiver CDR
Lock Mode (4)
in Manual
functional modes
All supported
except PCIe
4–7.
4–8.
4–9.
4–11.
4–12.
4–13.
4–14.
4–15.
"Transmitter Only"
Channel (2)
Non-Bonded
Reset Sequence
Receiver CDR
Lock Mode (5)
in Automatic
"Receiver Only"
Channel
Receiver CDR
Lock Mode (6)
in Manual
PCI Express (PIPE)
Arria II Device Handbook Volume 2: Transceivers
Normal Operation
Compliance and
Initialization and
Phases (1)
Figure 4–2
Receiver CDR
Lock Mode (7)
in Automatic
and the associated
Transmitter" Channel
"Receiver and
Receiver CDR
Lock Mode (8)
in Manual
4–5
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