EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 116
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
201
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
853
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX45DF29I5N PDF datasheet #6
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- Download datasheet (22Mb)
5–12
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Table 5–8
Table 5–8. PLL Connectivity to GCLKs for Arria II GX Devices
Table 5–9. PLL Connectivity to the GCLK Networks for Arria II GZ Devices
Table 5–10
Table 5–10. RCLK Outputs from PLLs for Arria II GX Devices
Table 5–11. RCLK Outputs From the PLL Clock Outputs for Arria II GZ Device
GCLK[0..3]
GCLK[4..7]
GCLK[8..11]
GCLK[12..15]
GCLK[0..3]
GCLK[4..7]
GCLK[8..11]
GCLK[12..15]
Note to
(1) Only PLL counter outputs C0 - C3 can drive the GCLK networks.
RCLK[0..11]
RCLK[12..23]
RCLK[24..35]
RCLK[36..47]
RCLK[0..11]
RCLK[12..31]
RCLK[32..43]
RCLK[44..63]
Clock Network
Clock Resource
Table
Clock Resource
Clock Network
and
and
5–9:
Table 5–9
Table 5–11
v
—
—
—
L2
list the Arria II PLL connectivity to GCLK networks.
list how the PLL clock outputs connect to RCLK networks.
v
—
—
—
L2
L3
—
—
—
v
v
—
—
v
1
—
—
v
v
1
v
L3
—
—
—
B1
—
v
—
—
—
—
v
v
B1
—
v
—
—
—
—
2
v
v
2
Chapter 5: Clock Networks and PLLs in Arria II Devices
B2
v
PLL Number
—
—
—
PLL Number
B2
—
v
—
—
—
v
—
—
—
PLL Number
v
3
v
v
PLL Number
3
R2
—
—
v
—
R2
v
—
—
—
December 2010 Altera Corporation
Clock Networks in Arria II Devices
v
v
—
—
—
—
v
v
4
4
v
R3
—
—
—
R3
v
(Note 1)
—
—
—
—
—
—
—
—
v
—
v
5
5
T1
—
—
—
v
v
T1
—
—
—
—
—
—
v
—
—
v
—
6
v
T2
—
—
—
—
—
6
T2
—
v
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