EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 135
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Figure 5–25. Phase Relationship Between PLL Clocks in Zero Delay Buffer Mode for Arria II Devices
Note to
(1) The internal PLL clock output can lead or lag the external PLL clock outputs.
December 2010 Altera Corporation
Figure
5–25:
Figure 5–25
ZDB mode.
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port
Dedicated PLL
Clock Outputs (1)
External Feedback Mode
In external feedback mode, the external feedback input pin (fbin) is phase-aligned
with the clock input pin, as shown in
remove clock delay and skew between devices. This mode is supported on all
Arria II GZ PLLs.
In external feedback mode, the output of the M counter (FBOUT) feeds back to the PLL
fbin input (using a trace on the board) becoming part of the feedback loop. Also, use
one of the dual-purpose external clock outputs as the fbin input pin in this mode.
You must use the same I/O standard on the input clock, feedback input, and output
clocks. Left and right PLLs support this mode when using single-ended I/O
standards only.
shows an example waveform of the PLL clocks’ phase relationship in
Phase Aligned
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Figure
5–26. Aligning these clocks allows you to
5–31
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