EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 161

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6: I/O Features in Arria II Devices
I/O Standards Support
Table 6–2. I/O Standards and Voltage Levels for Arria II GZ Devices
December 2010 Altera Corporation
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVCMOS
1.8-V LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
3.0-V PCI
3.0-V PCI-X
SSTL-2 Class I, II
SSTL-18 Class I, II
SSTL-15 Class I
SSTL-15 Class II
HSTL-18 Class I, II
HSTL-15 Class I
HSTL-15 Class II
HSTL-12 Class I
HSTL-12 Class II
Differential SSTL-2
Class I, II
Differential SSTL-18
Class I, II
Differential SSTL-15
Class I
Differential SSTL-15
Class II
Differential HSTL-18
Class I, II
Differential HSTL-15
Class I
Differential HSTL-15
Class II
Differential HSTL-12
Class I
Differential HSTL-12
Class II
I/O Standard
(3)
Table 6–2
values for input and output V
PCI Rev 2.1
JESD8-16A
JESD8-16A
JESD8-16A
JESD8-16A
PCI-X Rev
JESD8-9B
JESD8-9B
JESD8-11
JESD8-12
JESD8-15
JESD8-15
Standard
JESD8-B
JESD8-6
JESD8-B
JESD8-5
JESD8-7
JESD8-6
JESD8-6
JESD8-6
JESD8-6
JESD8-6
Support
1.0
—
—
—
—
lists the supported I/O standards for Arria II GZ devices and the typical
I/O Banks
Column
3.0/2.5
3.0/2.5
3.0/2.5
1.8/1.5
1.8/1.5
Input Operation
1.2
3.0
3.0
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
Row I/O
3.0/2.5
3.0/2.5
3.0/2.5
1.8/1.5
1.8/1.5
Banks
1.2
3.0
3.0
CCIO
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
V
, V
CCIO
Arria II Device Handbook Volume 1: Device Interfaces and Integration
CCPD
(V)
I/O Banks
Column
Output Operation
(Note 1)
3.0
3.0
2.5
1.8
1.5
1.2
3.0
3.0
2.5
1.8
1.5
1.5
1.8
1.5
1.5
1.2
1.2
2.5
1.8
1.5
1.5
1.8
1.5
1.5
1.2
1.2
, V
R EF
, and board V
(Part 1 of 2)
Row I/O
Banks
1.2
3.0
2.5
3.0
3.0
2.5
1.8
1.5
3.0
1.8
1.5
1.8
1.5
1.2
2.5
1.8
1.5
1.8
1.5
1.2
—
—
—
—
—
—
V
Voltage)
CCPD
Driver
TT
(Pre-
3.0
3.0
2.5
2.5
2.5
2.5
3.0
3.0
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
.
(V)
Voltage)
V
(Input
REF
1.25
0.90
0.75
0.75
0.90
0.75
0.75
Ref
0.6
0.6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(V)
Termination
Voltage)
(Board
V
1.25
0.90
0.75
0.75
0.90
0.75
0.75
1.25
0.90
0.75
0.75
0.90
0.75
0.75
0.60
0.60
TT
0.6
0.6
—
—
—
—
—
—
—
—
6–3
(V)