EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 162
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX45DF29I5N PDF datasheet #6
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6–4
Table 6–2. I/O Standards and Voltage Levels for Arria II GZ Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
LVDS (4), (5),
RSDS (6), (7),
mini-LVDS (6), (7),
LVPECL
Notes to
(1) V
(2) Single-ended HSTL/SSTL, differential SSTL/HSTL, and LVDS input buffers are powered by V
(3) For more information about the 3.3-V LVTTL/LVCMOS standard supported in Stratix IV devices, refer to
(4) Column I/O banks support LVPECL I/O standards for input clock operation. Clock inputs on column I/Os are powered by V
(5) Column and row I/O banks support LVDS outputs using two single-ended output buffers, an external one-resistor (LVDS_E_1R), and a three-resistor
(6) Row I/O banks support RSDS and mini-LVDS I/O standards using a true LVDS output buffer without a resistor network.
(7) Column and row I/O banks support RSDS and mini-LVDS I/O standards using two single-ended output buffers with one-resistor (RSDS_E_1R and
(8) The emulated differential output standard that supports the tri-state feature includes: LVDS_E_1R, LVDS_E_3R, RSDS_E_1R, RSDS_E_3R,
(8)
buffers and true differential output buffers. Column I/O banks support true differential input buffers, but not true differential output buffers. I/O pins
are organized in pairs to support differential standards. Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers without
R
as differential clock inputs. They are powered by V
by V
(LVDS_E_3R) network.
mini-LVDS_E_1R) and three-resistor (RSDS_E_3R and mini-LVDS_E_3R) networks.
Mini_LVDS_E_1R, and Mini_LVDS_E_3R. For more information, refer to the
CCPD
I/O Standard
D
OCT support.
CCPD
Table
is either 2.5 or 3.0 V. For V
.
6–1:
f
(8)
(8)
For detailed electrical characteristics of each I/O standard, refer to the
Data
ANSI/TIA/
Standard
Support
EIA-644
Sheet.
—
—
—
CCIO
= 3.0 V, V
I/O Banks
Column
CCPD
Input Operation
CCIO
(2)
(2)
(2)
(4)
= 3.0 V. For V
when configured as single-ended clock inputs. Differential clock inputs in row I/Os are powered
Row I/O
Banks
2.5
(2)
(2)
(2)
CCIO
V
= 2.5 V or less, V
CCIO
(V)
I/O Banks
Column
I/O Buffer (ALTIOBUF) Megafunction User
Output Operation
(Note 1)
2.5
2.5
2.5
—
CCPD
(Part 2 of 2)
Row I/O
= 2.5 V.
CCPD
Banks
2.5
2.5
2.5
—
. Row I/O banks support both true differential input
Chapter 6: I/O Features in Arria II Devices
“3.3-V I/O Interface” on page
V
Voltage)
December 2010 Altera Corporation
CCPD
Driver
(Pre-
2.5
2.5
2.5
2.5
(V)
Voltage)
Guide.
V
(Input
I/O Standards Support
Arria II Devices
REF
Ref
CCCLKIN
—
—
—
—
(V)
when configured
Termination
6–13.
Voltage)
(Board
V
TT
—
—
—
—
(V)
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