EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 295
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Fast Passive Parallel Configuration
Figure 9–4. FPP Configuration Timing Waveform with Decompression and Design Security not Enabled
Notes to
(1) Use this timing waveform when you do not use the decompression and design security features.
(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic-high levels. When
(3) After power-up, the Arria II device holds nSTATUS low for the time of the POR delay.
(4) After power-up, before and during configuration, CONF_DONE is low.
(5) Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device.
(6) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(7) DATA[7..1] are available as user I/O pins after configuration. The state of these pins depends on the dual-purpose pin settings. For Arria II GX
December 2010 Altera Corporation
nCONFIG is pulled low, a reconfiguration cycle begins.
devices, DATA[0] is a dedicated pin that is used for both the PS and AS configuration modes and is not available as a user I/O pin after
configuration. For Arria II GZ devices, DATA[0] is available as a user I/O pin after configuration.
Figure
9–4:
CONF_DONE (4)
nSTATUS (3)
INIT_DONE
DATA[7..0]
nCONFIG
FPP Configuration Timing
Figure 9–4
MAX II device as an external host. This waveform shows timing when the
decompression and design security features are not enabled.
User I/O
DCLK
t
t
CF2CD
CFG
shows the timing waveform for an FPP configuration when using a
t
CF2ST1
t
CF2ST0
t
t
CF2CK
ST2CK
t
Byte 0 Byte 1 Byte 2 Byte 3
STATUS
High-Z
t
CH
t
CLK
t
DSU
t
CL
t
DH
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Byte n-2 Byte n-1
(5)
Byte n
t
CD2UM
(7)
User Mode
User Mode
(6)
(Note
1),
(2)
9–15
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