EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 398
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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1–12
Transmitter Channel Datapath
Figure 1–11. Transmitter Channel Datapath
Table 1–4. Transmitter Phase Compensation FIFO Modes for Arria II Devices
Arria II Device Handbook Volume 2: Transceivers
Low Latency
High Latency
Register
Notes to
(1) Automatically set when you select a protocol in the ALTGX MegaWizard Plug-In Manager.
(2) Pending characterization.
Fabric
FPGA
Table
Transmitter PCS
Mode
hard IP
PCIe
1–4:
f
This section describes the Arria II GX and GZ transmitter channel datapath
architecture. The sub-blocks in the transmitter datapath are described in order from
the TX phase compensation FIFO buffer at the FPGA fabric-to-transceiver interface to
the transmitter input buffer.
Figure 1–11
This section describes the transmitter PCS modules, which consists of the TX phase
compensation FIFO, byte serializer, and 8B/10B encoder.
The tx_digitalreset signal resets all modules in the transmitter PCS block.
For more information about the tx_digitalreset signal, refer to the
Power Down in Arria II Devices
TX Phase Compensation FIFO
This FIFO compensates for the phase difference between the low-speed parallel clock
and the FPGA fabric interface clock.
phase compensation FIFO.
4-words deep
8-words deep
Interface
FIFO Depth
PIPE
—
shows the transmitter channel datapath.
Compensation
2-to-3 parallel clock cycles
4-to-5 parallel clock cycles
TX Phase
FIFO
Latency Through FIFO
chapter.
1
Transmitter Channel PCS
Byte Serializer
Table 1–4
(2)
(2)
Chapter 1: Transceiver Architecture in Arria II Devices
lists the available modes for the TX
All functional modes except PCIe and
Applicable Functional Modes
8B/10 Encoder
Deterministic Latency
Deterministic Latency
December 2010 Altera Corporation
Transmitter Channel Datapath
PCIe
Transmitter Channel PMA
Reset Control and
Serializer
(1)
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