EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 409
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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Chapter 1: Transceiver Architecture in Arria II Devices
Receiver Channel Datapath
December 2010 Altera Corporation
Programmable Common Mode Voltage
The Arria II GX and GZ receivers have on-chip biasing circuitry to establish the
required common mode voltage at the receiver input that supports two common
mode voltage settings of 0.82 V and 1.1 V. You can select the voltage in the ALTGX
MegaWizard Plug-In Manager. For the I/O standards supported by each common
mode voltage setting, refer to
This feature is effective only if you use programmable OCT for the receiver input
buffers as well. If you use external termination, you must implement off-chip biasing
circuitry to establish the common mode voltage at the receiver input buffer.
AC and DC Coupling
A high-speed serial link can either be AC-coupled or DC-coupled, depending on the
serial protocol implementation. Most of the serial protocols require links to be
AC-coupled, protocols similar to SONET optionally allow DC coupling.
In an AC-coupled link, the AC-coupling capacitor blocks the transmitter DC common
mode voltage. The on-chip receiver termination and biasing circuitry automatically
restores the selected common mode voltage. AC-coupled links are required in GIGE,
PCIe, Serial RapidIO, SDI, and XAUI protocols.
Figure 1–25
Figure 1–25. AC-Coupled Link
In a DC-coupled link, the transmitter DC common mode voltage is seen unblocked at
the receiver input buffer. The link common mode voltage depends on the transmitter
common mode voltage and the receiver common mode voltage. The on-chip or
off-chip receiver termination and biasing circuitry must ensure compatibility between
the transmitter and the receiver common mode voltage.
TX Termination
Transmitter
shows an AC-coupled link.
V
TX
CM
Table
Transmission Medium
Transmission Medium
1–6.
AC-Coupling
AC-Coupling
Capacitor
Capacitor
Arria II Device Handbook Volume 2: Transceivers
V
RX
CM
RX Termination
Receiver
1–23
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