EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 474
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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1–88
Figure 1–84. PCIe Reverse Parallel Loopback Mode Datapath
Arria II Device Handbook Volume 2: Transceivers
Fabric
FPGA
PCIe (Reverse Parallel Loopback)
Built-In Self Test (BIST) and Pseudo Random Binary Sequence (PRBS)
PCIe reverse parallel loopback is only available in PCIe functional mode for the Gen1
and Gen2 data rates. As shown in
the receiver CDR, deserializer, word aligner, and rate match FIFO buffer. The data is
then looped back to the transmitter serializer and transmitted out through the
tx_dataout port. The received data is also available to the FPGA fabric through the
rx_dataout port. This loopback mode is compliant with the PCIe Base Specification
2.0. To enable PCIe reverse parallel loopback mode, assert the tx_detectrxloopback
port.
Each transceiver channel in Arria II GX and GZ devices contain a pattern generator
and a pattern verifier circuit. Using these patterns, you can verify the functionality of
the functional blocks in the transceiver channel without requiring user logic. The
functionality is provided as an optional mechanism for debugging transceiver
channels. To use the Arria II GX and GZ pattern generator and verifier, use the pattern
BIST and PRBS sub-protocols under Basic functional mode.
Compensation
wrclk
TX Phase
FIFO
rdclk
wrclk
Byte Serializer
Receiver Channel PCS
Transmitter Channel PCS
rdclk
Figure
1–84, the received serial data passes through
Chapter 1: Transceiver Architecture in Arria II Devices
8B/10B Encoder
Reverse Parallel
Loopback Path
December 2010 Altera Corporation
Transmitter Channel
Receiver Channel
PMA
PMA
Test Modes
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