EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 586
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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4–12
Figure 4–7. Sample Reset Sequence of Receiver-Only Channel—Receiver CDR in Manual Lock Mode
Arria II Device Handbook Volume 2: Transceivers
Reset Signals
CDR Control Signals
Output Status Signals
rx_analogreset
rx_locktorefclk
rx_digitalreset
rx_locktodata
rx_pll_locked
Receiver Only Channel—Receiver CDR in Manual Lock Mode
This configuration contains only a receiver channel. If you create a Receiver Only
instance in the ALTGX MegaWizard Plug-In Manager with the receiver CDR in
manual lock mode, use the reset sequence shown in
As shown in
CDR in manual lock mode:
1. After power up, assert rx_analogreset for a minimum period of two parallel
2. Keep the rx_digitalreset and rx_locktorefclk signals asserted and the
3. After de-assertion of the busy signal, de-assert the rx_analogreset signal, after
4. Wait at least 15 s (the time between markers 3 and 4) after the rx_pll_locked
5. De-assert rx_digitalreset at least 4 s (the time between markers 4 and 5) after
busy
clock cycles (the time between markers 1 and 2).
rx_locktodata signal de-asserted during this time period.
which the receiver CDR starts locking to the receiver input reference clock because
the rx_locktorefclk signal is asserted.
signal goes high, and then de-assert the rx_locktorefclk signal. At the same time,
assert the rx_locktodata signal (marker 4). At this point, the receiver CDR enters
lock-to-data mode and the receiver PLL starts locking to the received data.
asserting the rx_locktodata signal.
Figure
Two parallel clock cycles
1
4–7, perform the following reset sequence steps for the receiver
2
3
Chapter 4: Reset Control and Power Down in Arria II Devices
15 μs
4
4
4 μs
5
Figure
4–7.
December 2010 Altera Corporation
Transceiver Reset Sequences
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