EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 95
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
Figure 4–16. Four-Multiplier Adder Mode Shown for Half-DSP Block
Note to
(1) Block output for accumulator overflow and saturate overflow.
December 2010 Altera Corporation
Figure
Four-Multiplier Adder
4–16:
dataa_0[ ]
datab_0[ ]
dataa_1[ ]
datab_1[ ]
datab_2[ ]
dataa_3[ ]
datab_3[ ]
dataa_2[ ]
In the four-multiplier adder configuration shown in
implement 2 four-multiplier adders (1 four-multiplier adder per half-DSP block).
These modes are useful for implementing one-dimensional and two-dimensional
filtering applications. The four-multiplier adder is performed in two addition stages.
The outputs of two of the four multipliers are initially summed in the two first-stage
adder blocks. The results of these two adder blocks are then summed in the
second-stage adder block to produce the final four-multiplier adder result, as shown
in
Four-multiplier adder mode supports the rounding and saturation logic unit. You can
use the pipeline registers and output registers within the DSP block to pipeline the
multiplier-adder result, increasing the performance of the DSP block.
Equation 4–2 on page 4–4
Half-DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
output_saturate
output_round
+
+
and
signa
signb
Equation 4–3 on page
Arria II Device Handbook Volume 1: Device Interfaces and Integration
+
Figure
4–5.
overflow (1)
4–16, the DSP block can
result[ ]
4–23
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