EPF10K130EQI240-2 Altera, EPF10K130EQI240-2 Datasheet - Page 52

• Manufacturer Part Number: EPF10K130EQI240-2
• Description: IC FLEX 10KE FPGA 130K 240-PQFP
• Manufacturer: Altera
• Series: FLEX-10KE®r

Specifications of EPF10K130EQI240-2

• Number Of Logic Elements/cells: 6656
• Number Of Labs/clbs: 832
• Total Ram Bits: 65536
• Number Of I /o: 186
• Number Of Gates: 342000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 240-MQFP, 240-PQFP
• Family Name: FLEX 10KE
• Number Of Usable Gates: 130000
• Number Of Logic Blocks/elements: 6656
• # Registers: 186
• # I/os (max): 186
• Frequency (max): 333.33MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 6656
• Ram Bits: 65536
• Device System Gates: 342000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-2206

FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 23. Output Drive Characteristics of FLEX 10KE Devices
Note:
(1)
Timing Model
52
These are transient (AC) currents.
Typical I
Output
Current (mA)
O
30
20
10
90
80
70
60
50
40
V
The continuous, high-performance FastTrack Interconnect routing
resources ensure predictable performance and accurate simulation and
timing analysis. This predictable performance contrasts with that of
FPGAs, which use a segmented connection scheme and therefore have
unpredictable performance.
Device performance can be estimated by following the signal path from a
source, through the interconnect, to the destination. For example, the
registered performance between two LEs on the same row can be
calculated by adding the following parameters:
The routing delay depends on the placement of the source and destination
LEs. A more complex registered path may involve multiple combinatorial
LEs between the source and destination LEs.
O
1
V
V
Room Temperature
Output Voltage (V)
CCINT
CCIO
LE register clock-to-output delay (t
Interconnect delay (t
LE look-up table delay (t
LE register setup time (t
= 2.5
= 2.5
2
V
I
OH
V
I
OL
3
Typical I
Output
Current (mA)
SAMEROW
O
SU
LUT
)
)
30
20
10
90
80
70
60
50
40
Note (1)
)
CO
V
)
O
1
Output Voltage (V)
2
V
V
Room Temperature
I
Altera Corporation
OL
CCINT
CCIO
3
I
OH
= 3.3
= 2.5
V
V