EP1SGX25DF1020C7N Altera, EP1SGX25DF1020C7N Datasheet - Page 96
EP1SGX25DF1020C7N
Manufacturer Part Number
EP1SGX25DF1020C7N
Description
IC STRATIX GX FPGA 25K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX25DF1020C7N
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
607
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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TriMatrix Memory
4–30
Stratix GX Device Handbook, Volume 1
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for
applications where a large volume of data must be stored on-chip. Each
block contains 589,824 RAM bits (including parity bits). The M-RAM
block can be configured in the following modes:
■
■
■
■
You cannot use an initialization file to initialize the contents of a M-RAM
block. All M-RAM block contents power up to an undefined value. Only
synchronous operation is supported in the M-RAM block, so all inputs
are registered. Output registers can be bypassed. The memory address
and output width can be configured as 64K × 8 (or 64K × 9 bits), 32K × 16
(or 32K × 18 bits), 16K × 32 (or 16K × 36 bits), 8K × 64 (or 8K × 72 bits), and
4K × 128 (or 4K × 144 bits). The 4K × 128 configuration is unavailable in
true dual-port mode because there are a total of 144 data output drivers
in the block. Mixed-width configurations are also possible, allowing
different read and write widths.
possible M-RAM block configurations:
64K
32K
16K
8K
4K
Table 4–7. M-RAM Block Configurations (Simple Dual-Port)
Read Port
×
×
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO RAM
×
×
×
72
144
9
18
36
64K × 9
v
v
v
v
32K × 18
v
v
v
v
Tables 4–7
Write Port
16K × 36
v
v
v
v
and
4–8
summarize the
8K × 72
v
v
v
v
Altera Corporation
February 2005
4K × 144
v
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