EP1S25F1020C5N Altera, EP1S25F1020C5N Datasheet - Page 86
EP1S25F1020C5N
Manufacturer Part Number
EP1S25F1020C5N
Description
IC STRATIX FPGA 25K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F1020C5N
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
706
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
25660
# I/os (max)
706
Frequency (max)
500MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S25F1020C5N
Manufacturer:
ALTERA
Quantity:
20 000
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Digital Signal Processing Block
Figure 2–41. DSP Block Interface to Interconnect
2–72
Stratix Device Handbook, Volume 1
C4 and C8
Interconnects
LAB
DSP Block to
LAB Row Interface
Block Interconnect Region
Direct Link Interconnect
from Adjacent LAB
10
A bus of 18 control signals feeds the entire DSP block. These signals
include clock[0..3] clocks, aclr[0..3] asynchronous clears,
ena[1..4] clock enables, signa, signb signed/unsigned control
signals, addnsub1 and addnsub3 addition and subtraction control
signals, and accum_sload[0..1] accumulator synchronous loads. The
Row Interface
18
3
Block
18 Inputs per Row
R4 and R8 Interconnects
10
9
Control
[17..0]
DSP Block
Row Structure
[17..0]
18 Outputs per Row
Nine Direct Link Outputs
to Adjacent LABs
18
18
9
Altera Corporation
Direct Link Interconnect
from Adjacent LAB
July 2005
LAB
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