EP1S40F1020C6N Altera, EP1S40F1020C6N Datasheet - Page 109
EP1S40F1020C6N
Manufacturer Part Number
EP1S40F1020C6N
Description
IC STRATIX FPGA 40K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S40F1020C6N
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
41250
# I/os (max)
773
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
41250
Ram Bits
3423744
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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Figure 2–56. External Clock Outputs for Enhanced PLLs 11 & 12
Note to
(1)
Altera Corporation
July 2005
Counter
g 0
For PLL 11, this pin is CLK13n; for PLL 12 this pin is CLK7n.
Figure
From Internal
Logic or IOE
2–56:
Enhanced PLLs 11 and 12 support one single-ended output each (see
Figure
Therefore, to minimize jitter, do not place switching I/O pins next to this
output pin.
Stratix devices can drive any enhanced PLL driven through the global
clock or regional clock network to any general I/O pin as an external
output clock. The jitter on the output clock is not guaranteed for these
cases.
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-3 Class I
SSTL-3 Class II
AGP (1× and 2× )
CTT
Table 2–20. I/O Standards Supported for Enhanced PLL Pins (Part 2 of 2)
2–56). These outputs do not have their own VCC and GND signals.
I/O Standard
INCLK
v
v
v
v
v
v
v
v
v
v
v
Stratix Device Handbook, Volume 1
FBIN
v
v
v
v
v
v
v
v
v
v
v
Input
or CLK6n, I/O, PLL12_OUT (1)
PLLENABLE
CLK13n, I/O, PLL11_OUT
Stratix Architecture
EXTCLK
Output
v
v
v
v
v
v
v
v
v
v
v
2–95
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