EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 115
Manufacturer Part Number
IC STRATIX FPGA 30K LE 780-FBGA
Specifications of EP1S30F780I6N
Number Of Logic Elements/cells
Number Of Labs/clbs
Total Ram Bits
Number Of I /o
Voltage - Supply
1.425 V ~ 1.575 V
-40°C ~ 100°C
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
Figure 2–58. Stratix Device Fast PLL
regional clock (1)
The global or regional clock input can be driven by an output from another PLL or any dedicated CLK or FCLK pin.
It cannot be driven by internally-generated global signals.
In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix devices only
support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
This signal is a high-speed differential I/O support SERDES control signal.
Clock Multiplication & Division
Stratix device fast PLLs provide clock synthesis for PLL output ports
using m/(post scaler) scaling factors. The input clock is multiplied by the
m feedback factor. Each output port has a unique post scale counter to
divide down the high-frequency VCO. There is one multiply divider, m,
per fast PLL with a range of 1 to 32. There are two post scale L dividers
for regional and/or LVDS interface clocks, and g0 counter for global clock
output port; all range from 1 to 32.
In the case of a high-speed differential interface, set the output counter to
1 to allow the high-speed VCO frequency to drive the SERDES. When
used for clocking the SERDES, the m counter can range from 1 to 30. The
VCO frequency is equal to f
300 and 1000 MHz.
VCO Phase Selection
Selectable at each PLL
×m, where VCO frequency must be between
Stratix Device Handbook, Volume 1