EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 117

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S30F780I6N
Manufacturer:
ALTERA
Quantity:
996
Part Number:
EP1S30F780I6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S30F780I6N
Manufacturer:
ALTERA
0
Altera Corporation
July 2005
Table 2–23
when using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology.
External Clock Outputs
Each fast PLL supports differential or single-ended outputs for source-
synchronous transmitters or for general-purpose external clocks. There
are no dedicated external clock output pins. Any I/O pin can be driven
by the fast PLL global or regional outputs as an external output pin. The
I/O standards supported by any particular bank determines what
standards are possible for an external clock output driven by the fast PLL
in that bank.
Phase Shifting
Stratix device fast PLLs have advanced clock shift capability that enables
programmable phase shifts. You can enter a phase shift (in degrees or
time units) for each PLL clock output port or for all outputs together in
one shift. You can perform phase shifting in time units with a resolution
range of 125 to 416.66 ps. This resolution is a function of the VCO period,
with the finest step being equal to an eighth (×0.125) of the VCO period.
Note to
(1)
SSTL-2 Class II
SSTL-3 Class I
SSTL-3 Class II
AGP (1× and 2× )
CTT
CLK0, CLK2, CLK9, CLK11,
FPLL7CLK, FPLL8CLK, FPLL9CLK,
FPLL10CLK
CLK1, CLK3, CLK8, CLK10
Table 2–22. Fast PLL Port I/O Standards (Part 2 of 2)
Table 2–23. LVDS Performance on Fast PLL Input
See the chapter DC & Switching Characteristics of the Stratix Device Handbook,
Volume 1 for more information.
Table
Fast PLL Clock Input
shows the performance on each of the fast PLL clock inputs
I/O Standard
2–23:
Stratix Device Handbook, Volume 1
Maximum Input Frequency (MHz)
INCLK
v
v
v
v
717(1)
Input
645
Stratix Architecture
PLLENABLE
2–103