EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 122

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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0
I/O Structure
Figure 2–62. Signal Path through the I/O Block
2–108
Stratix Device Handbook, Volume 1
Interconnect
From Logic
From I/O
To Logic
Array
Array
Row or Column
io_bclk[3..0]
io_boe[3..0]
io_dataout0
io_dataout1
io_bce[3..0]
io_bclr[3..0]
io_cce_out
io_clk[7..0]
io_datain0
io_datain1
io_cce_in
io_cclk
io_coe
io_cclr
Stratix devices have an I/O interconnect similar to the R4 and C4
interconnect to drive high-fanout signals to and from the I/O blocks.
There are 16 signals that drive into the I/O blocks composed of four
output enables io_boe[3..0], four clock enables io_bce[3..0], four
clocks io_bclk[3..0], and four clear signals io_bclr[3..0]. The
pin’s datain signals can drive the IO interconnect, which in turn drives
the logic array or other I/O blocks. In addition, the control and data
signals can be driven from the logic array, providing a slower but more
flexible routing resource. The row or column IOE clocks, io_clk[7..0],
provide a dedicated routing resource for low-skew, high-speed clocks.
I/O clocks are generated from regional, global, or fast regional clocks (see
“PLLs & Clock Networks” on page
signal paths through the I/O block.
Selection
Control
Signal
oe
ce_in
ce_out
aclr/apreset
sclr/spreset
clk_in
clk_out
To Other
IOEs
2–73).
Figure 2–62
IOE
illustrates the
Altera Corporation
July 2005