EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 128

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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0
I/O Structure
Figure 2–67. Stratix IOE in DDR Output I/O Configuration
Notes to
(1)
(2)
2–114
Stratix Device Handbook, Volume 1
Column or Row
Interconnect
All input signals to the IOE can be inverted at the IOE.
The tristate is by default active high. It can, however, be designed to be active low.
I/O Interconnect
Figure
[15..0]
IOE_CLK[7..0]
2–67:
clkout
aclr/prn
sclr
Chip-Wide Reset
Register Delay
Register Delay
Logic Array
Enable Clock
Enable Delay
Enable Delay
Logic Array
Output Clock
to Output
to Output
Output
Output Register
Output Register
OE Register
OE Register
ENA
Notes
D
CLRN/PRN
D
CLRN/PRN
D
CLRN/PRN
D
CLRN/PRN
ENA
ENA
ENA
Q
Q
Q
Q
(1),
(2)
Drive Strength Control
Used for
DDR SDRAM
Pin Delay
Output
Open-Drain Output
Slew Control
clk
t
ZX
Output
Delay
OE Register
t
CO
Delay
V
CCIO
Altera Corporation
V
CCIO
Optional
PCI Clamp
Bus-Hold
Circuit
Programmable
Pull-Up
Resistor
July 2005