EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 158

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S30F780I6N
Manufacturer:
ALTERA
Quantity:
996
Part Number:
EP1S30F780I6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S30F780I6N
Manufacturer:
ALTERA
0
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
3–4
Stratix Device Handbook, Volume 1
Figure 3–1
Figure 3–1. Stratix JTAG Waveforms
Table 3–4
devices.
t
t
t
t
t
t
t
t
t
t
t
t
t
Captured
Symbol
JCP
JCH
JCL
JPSU
JPH
JPCO
JPZX
JPXZ
JSSU
JSH
JSCO
JSZX
JSXZ
Table 3–4. Stratix JTAG Timing Parameters & Values
Driven
Signal
Signal
to Be
to Be
TMS
TDO
TCK
TDI
shows the JTAG timing parameters and values for Stratix
TCK
TCK
TCK
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
shows the timing requirements for the JTAG signals.
t
clock period
clock high time
clock low time
JCH
t
t
JPZX
JSZX
t
JCP
t
JSSU
t
JCL
Parameter
t
JSH
t
t
JPCO
JSCO
t
JPSU
t
t
JSXZ
JPH
Altera Corporation
Min
100
50
50
20
45
20
45
t
JPXZ
Max
25
25
25
35
35
35
July 2005
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns