EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 161

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Altera Corporation
July 2005
Configuring Stratix FPGAs with JRunner
JRunner is a software driver that configures Altera FPGAs, including
Stratix FPGAs, through the ByteBlaster II or ByteBlasterMV cables in
JTAG mode. The programming input file supported is in Raw Binary File
(.rbf) format. JRunner also requires a Chain Description File (.cdf)
generated by the Quartus II software. JRunner is targeted for embedded
JTAG configuration. The source code is developed for the Windows NT
operating system (OS), but can be customized to run on other platforms.
For more information on the JRunner software driver, see the JRunner
Software Driver: An Embedded Solution to the JTAG Configuration
White Paper and the source files on the Altera web site (www.altera.com).
Configuration Schemes
You can load the configuration data for a Stratix device with one of five
configuration schemes (see
application. You can use a configuration device, intelligent controller, or
the JTAG port to configure a Stratix device. A configuration device can
automatically configure a Stratix device at system power-up.
Multiple Stratix devices can be configured in any of five configuration
schemes by connecting the configuration enable (nCE) and configuration
enable output (nCEO) pins on each device.
Partial Reconfiguration
The enhanced PLLs within the Stratix device family support partial
reconfiguration of their multiply, divide, and time delay settings without
reconfiguring the entire device. You can use either serial data from the
logic array or regular I/O pins to program the PLL’s counter settings in a
serial chain. This option provides considerable flexibility for frequency
Configuration device
Passive serial (PS)
Passive parallel
asynchronous (PPA)
Fast passive parallel
JTAG
Table 3–5. Data Sources for Configuration
Configuration Scheme
Table
Enhanced or EPC2 configuration device
MasterBlaster, ByteBlasterMV, or ByteBlaster II
download cable or serial data source
Parallel data source
Parallel data source
MasterBlaster, ByteBlasterMV, or ByteBlaster II
download cable, a microprocessor with a Jam or
JBC file, or JRunner
3–5), chosen on the basis of the target
Stratix Device Handbook, Volume 1
Data Source
Configuration & Testing
3–7